question about testbench

[Altera_Forum]

Hi all, 

  I am trying to write a VHDL testbench. I am wondering what kind of file I should create for the testbench, VHDL script file or anything else? If it is VHDL script file, how does the simulator could distinguish the VHDL entity file between VHDL testbench file?Thanks

[Altera_Forum]

There no such thing as a VHDL script file. a testbench is just a VHDL file. You instantiate the unit under test inside the testbench.

[Altera_Forum]

You should read some things about VHDL testbenches. A good point to start would be to Google for "VHDL testbench". There is a good explanation on the Doulos website.