"The design unit was not found"

Altera_Forum · ‎10-03-2017

Hi!

I am a complete noobie and have been directed to use this software for a class. I keep getting this error and the professor and IT department have been zero help and just tell me they do not know and to figure it out. I've seen a lot of similar posts with the same error but to be honest I have no idea what they are talking about for solutions. Can anyone please tell me how to fix this and what a design unit is?

# Reading C:/intelFPGA_lite/17.0/modelsim_ase/tcl/vsim/pref.tcl# do myFullAdder01_run_msim_rtl_verilog.do# if {[file exists rtl_work]} {# vdel -lib rtl_work -all# }# vlib rtl_work# vmap work rtl_work# Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016# vmap work rtl_work # Copying C:/intelFPGA_lite/17.0/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini# Modifying modelsim.ini# # vlog -sv -work work +incdir+//Mac/Home/Desktop/EGR-2440/Altera {//Mac/Home/Desktop/EGR-2440/Altera/myFullAdder01.sv}# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016# Start time: 18:56:03 on Oct 03,2017# vlog -reportprogress 300 -sv -work work "+incdir+//Mac/Home/Desktop/EGR-2440/Altera" //Mac/Home/Desktop/EGR-2440/Altera/myFullAdder01.sv # -- Compiling module myFullAdder01# # Top level modules:# myFullAdder01# End time: 18:56:03 on Oct 03,2017, Elapsed time: 0:00:00# Errors: 0, Warnings: 0#

vlog -reportprogress 300 -work work //Mac/Home/Desktop/EGR-2440/Altera/testMyFullAdder01.sv# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016# Start time: 18:56:29 on Oct 03,2017# vlog -reportprogress 300 -work work //Mac/Home/Desktop/EGR-2440/Altera/testMyFullAdder01.sv # -- Compiling module testMyFullAdder# # Top level modules:# testMyFullAdder# End time: 18:56:29 on Oct 03,2017, Elapsed time: 0:00:00# Errors: 0, Warnings: 0

vsim work.testMyFullAdder# vsim work.testMyFullAdder # Start time: 18:56:42 on Oct 03,2017# Loading sv_std.std# Loading work.testMyFullAdder# ** Error: (vsim-3033) //Mac/Home/Desktop/EGR-2440/Altera/testMyFullAdder01.sv(6): Instantiation of 'myFullAdder' failed. The design unit was not found.# Time: 0 ps Iteration: 0 Instance: /testMyFullAdder File: //Mac/Home/Desktop/EGR-2440/Altera/testMyFullAdder01.sv# Searched libraries:# //Mac/Home/Desktop/EGR-2440/Altera/simulation/modelsim/rtl_work# Error loading design# End time: 18:56:43 on Oct 03,2017, Elapsed time: 0:00:01# Errors: 1, Warnings: 0

Altera_Forum · ‎10-03-2017

A design unit, in the case of Verilog or SystemVerilog, is the "module" you created in your .sv file. The error is saying that ModelSim can't find this design unit, which is odd because it's compiling it just above. There could be something wrong with the instantiation of the myFullAdder01 module in testMyFullAdder01. Can you post some code?

Altera_Forum · ‎10-04-2017

myFullAdder01.sv

*

module myFullAdder01# (parameter N=4)

(output logic [N-1:0] Sum, output logic Cout,

input logic [N-1:0] A, B, input logic Cin);

always_comb

{Cout, Sum} = A + B + Cin;

endmodule

*

testMyFullAdder01.sv

*

module testMyFullAdder;

parameter N = 4;

logic Cin, Cout;

logic [N-1:0] Sum, A, B;

myFullAdder# (N) s0 (.*);

initial

begin

Cin = 0;

A = 0;

B = 0;

# 5ns A = 15;

# 5ns Cin = 1;

# 5ns A = 7;

# 5ns B = 15;

# 5ns Cin = 0;

end

endmodule

Altera_Forum · ‎10-04-2017

You called the module myFullAdder01 but instantiated it as myFullAdder.

Altera_Forum · ‎10-04-2017

Thank you!!!!