- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
hi, everyone, I'm new to verilog. I got a problem when I try to use "+" operator.
I was doing a accumulate sum by add new result to old result. The simulation gives me correct result everytime, but the actual result from FPGA output looks like this: Current Result: 1 16 7 8 2 5 Previous Result: 0 0 16 22 30 32 Final Result 0 16 22 30 32 36 It is clearly that something wrong with the odd numbers. Here is my code about this three data.
reg final_result;
reg previous_result;
reg counter;
always @ (*) begin
case(fsm_cs)
FSM_START: begin
counter <= 0;
final_result <= 0;
(to FSN_1)
end
FSM_1: begin
previous_result <= final_result;
(begin some calculation)
end
..........
FSM: begin
counter <= w_result;
final_result <= w_result + previous_result;
(back to FSM_1)
end
If anyone knows what's wrong or I have confused you please let me know.
Link Copied
2 Replies
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Is that all your codes? what is the ........ ?
How is your w_result get assigned? and did you declare your w_result?- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I more the code is asynchronous. Where do all of the inputs come from? Why I'd this design not synchronous?
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page