selecting parameter based on reg value - verilog

[Altera_Forum]

Hi , 

 I have a set of parameters ( constants ) . I want to select one parameter at a time based on a register value (ex. reg [3:0] sel_value ) .  Or   i need to conditionally instantiate a module .  ex .  if ( some reg value ) ---> module1 (parameter1) module1_inst () ;  else module1 (parameter2) module1_inst () ;   Please guide me with the above as i am not able to figure out the solution .   Thanks in advance

[Altera_Forum]

The reg value can to be fed to the module as input port to allow selection of a specific parameter inside the module. Or select the parameter outside the module and give the actual paramter value to the modulethrough a port.

[Altera_Forum]

THanks for the reply . Can you please suggest me with an example or sample code ?

[Altera_Forum]

You can't select a parameter for a module override dynamically using a variable. Parameter values can only be made up of expressions of constants and other parameters. Did you really mean sel_value is the output of a register, or can it be another constant parameter? 

In any case, you have three choices of how you can represent your set of parameters 

1. If you can use SystemVerilog (yes if you are using ModelSim; no if you are synthesizing and your synthesis tool does not support SV yet), You can declare a array of constants: parameter int my_constants
2. You can concatenate your constants into one big vector and then do a part select to get the constant you want: parameter reg
3. You can declare as many constants you need as individual parameters to the module, and then use a case statement to select which parameter you want. 

 If sel_value is another parameter, then you can do module1# (my_constants) module1_inst(); // SystemVerilog module1# (my_constants) module1_inst(); // Verilog vector case (sel_value) // conditional generate block 0: module1# (constant0) module1_inst(); 1: module1# (constant1) module1_inst(); 2: module1# (constant2) module1_inst(); 3: module1# (constant3) module1_inst(); endcaseIf sel_value is a register, the you will have to pass both the parameter(s) and sel_value to the module, and do the selection inside the module. module1# (my_constants) module1_inst(sel_value); // SystemVerilog or Verilog vector module1# (constant1,constant2,constant3,constant4) module1_inst(sel_value); // case statement inside module1

[Altera_Forum]

Hi dave_59 , 

 Thanks for the reply .sel_value is a register . i am trying out with the solution . I didnt understood the below suggestion given by you    --- Quote Start ---   module1# (constant1,constant2,constant3,constant4) module1_inst(sel_value); // case statement inside module1  --- Quote End ---    did you mean , in module1 i have a case statement like the one below  parameter selected_value =100 ; case(sel_value) 000: selected_value = constant1 ; 111:selected_value = constant2 ; etc   But again selected_value is a parameter(constant) value and cannot be assigned in case statement ?

[Altera_Forum]

You cannot dynamically change the value of a parameter. Just like you can have constant array and then dynamically select an element, you could have a function call with a case statement inside it, or you could put the case statement inside an always block.