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Altera_Forum
Honored Contributor I
1,323 Views

set false path between clocks

Hi there 

 

If I have clock domain crossing in my design, should I set all paths between the two clocks as false path ? 

I'm working on a design and got setup&hold violations on a path crossing between the two domains. In time quest anaylzer I right-clicked the path and chose set false path between clocks. The SDC file was updated. I recompiled the project and got the same violation between the same nodes ! 

 

Am I missing something ? 

How can I check if a constraint is ignored or not ? May be the false path constraint is ignored. 

 

The two clocks are generated from different PLLs. They are completely unrelated, each of them is driven from a different oscillators. Please help, I got sick of this issue :mad:
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1 Reply
Altera_Forum
Honored Contributor I
55 Views

So there's no way they can be synchronously analyzed, so yes, they need to be cut. 

Just as importantly(if not more so), your design needs to know they're being transferred asynchronously. For example, if both clocks were 100MHz, but just coming from different sources, and you try to transfer a 16-bit bus between the two domains, you will get garbage on the other side, as bits will be captured from different words(or bits will got metastable). The real question is if you designed for these transfers to be asynchronous. If so, then cut them. 

When making the change to the .sdc, do not re-compile to see if it took. Launch the TQ GUI, and do a report_timing on the paths. You should see them get reported. Then modify your .sdc to cut the timing. Double-click Reset Design, and then re-run your report_timing command(click the up arrow to get it from the log history). It should come back and say No Paths to Report. That means it was cut, and you're able to do a full compile to see how it affects place-and-route. But if the path shows up, you'll need to debug. In your case the false path was ignored, was applied to the wrong path, etc. I can't say for sure what happened though.