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Altera_Forum
Honored Contributor I
1,311 Views

setting placement constraints in Quartus

Hi everybody, 

I am new with Quartus. I want to set some placement constraints on some logic blocks of the FPGA. For example, I want to prohibit some sites (ALM, block RAMs,...) and tell the tool to do not place any thing on these sites. Additionally, I want to force the tool to place some modules in a specified location (a rectangular region in the target FPGA). Is this capabilities available in Quartus?  

 

Thanks in advance, 

farzian
0 Kudos
4 Replies
Altera_Forum
Honored Contributor I
110 Views

Hi,  

 

 

I think "Partition planner" and "Logilock regions" in Quatus is what you are looking for, but these features are only available in Quartus standard and Pro editions.
Altera_Forum
Honored Contributor I
110 Views

Yes, you need to set LogicLock regions in the Chip Planner.

Altera_Forum
Honored Contributor I
110 Views

Hi Farzian, 

 

Yes, you can assign logic functions to physical resources on the device, using location assignments with the Assignment Editor or the Chip Planner and logic lock function. 

For more information click 1 (https://www.youtube.com/watch?v=tlhogcw7vz4) 2 (https://www.youtube.com/watch?v=l_cxszbbvoo

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
110 Views

Afaik, you cannot lock areas of the chip to prevent their use - just reserve areas/specific logic elements for specific entities/logic elements that give priority to the blocks you specify. If they are not used by this logic, then the fitter is free to put something else there. 

 

But why are you attempting to do this? unless you have some timing issues, its better to let the tool do the placement.
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