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setup and hold time with set_input_delay

Altera_Forum
Honored Contributor II
‎03-10-2009 09:32 AM
9,051 Views

Hello, 

 

I have some problem understanding the set_input_delay min and max 

constraint. 

Assume that you have an interface that is connected to an FPGA. 

This interface has a clock (Clk) and a databus (DB). 

The datavalid window is centered around the rising edge of Clk. Assume 

a setup time of 1ns and a hold time of 2 ns. The clk period is 10 ns. 

How should I constrain this with the set_input_delay command? 

 

thanks for helping me,
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Altera_Forum
Honored Contributor II
‎09-16-2011 06:48 PM
420 Views

Rysc, thank you kindly for your posts and clearing up IO constraints. The Quartus Documentation is extremely shotty. Thanks again.

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