several warnings using altlvds

[Altera_Forum]

Hi all, 

 i am trying to implement an receiving interface to an ADC (TI ADS6444) using Megafunction ALTLVDS/ALTLVDS_RX.  I have created 2 projects one in Quartus 9.1 SP2 the other in 10.1 SP1. Both share the same problems.  options: 700 Mbps, 7 bit, 4 channels (for the beginning), odd RAM buffer, internal PLL, 90 degrees phase alignment, using bitclk as inclk 350 MHz  In sdc file i just use: "derive_pll_clocks" and "derive_clock_uncertainty".    I am getting several warnings that i cannot interpret.   1)  Warning: Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.  name: PLL Compensation ignored entity: rx2_lvds_ddio_in ignored to: ddio_h_reg* ignored value: on ignored source: compiler or hdl assignment  2)  Warning: PLL cross checking found inconsistent PLL clock settings:  Warning: Clock: rx_inst|altlvds_rx_component|auto_generated|lvds_rx_pll|clk[0] with master clock period: 1.000 found on PLL node: rx_inst|altlvds_rx_component|auto_generated|lvds_rx_pll|clk[0] does not match the master clock period requirement: 2.857  Warning: Clock: rx_inst|altlvds_rx_component|auto_generated|lvds_rx_pll|clk[1] with master clock period: 1.000 found on PLL node: rx_inst|altlvds_rx_component|auto_generated|lvds_rx_pll|clk[1] does not match the master clock period requirement: 2.857  Warning: Clock: rx_inst|altlvds_rx_component|auto_generated|lvds_rx_pll|clk[2] with master clock period: 1.000 found on PLL node: rx_inst|altlvds_rx_component|auto_generated|lvds_rx_pll|clk[2] does not match the master clock period requirement: 2.857  3)  Critical Warning: Timing requirements not met  For all three models (slow, fast, 85C) there are negative setup slacks.    Maybe one of you knows something about that warnings. Whether they can be ignored or not. Thanks a lot!

[Altera_Forum]

--- Quote Start ---  In sdc file i just use: "derive_pll_clocks" and "derive_clock_uncertainty".  --- Quote End ---   You also need to create your base clock(s), otherwise TimeQuest assumes it is 1.0 GHz! Hence the warnings in your section 2) and obviously you won't be able to make any timing as documented in your section 3). I don't know how to interpret your warning 1) as this may be a 'design' issue but could also be a valid 'ignored assignment'. It is a good idea to work to keep the generated warnings to a minimum, I'd say to zero but when using third-party or even Altera IP this is not always possible.

[Altera_Forum]

Thank you josyb! 

 Adding the following line eliminated the warning 2) and reduced number of points where negative slacks occure 3).  create_clock -add -period 2.857 -name clock_name [get_ports adc_clk]   Warnings 1) still appears.

[Altera_Forum]

--- Quote Start ---  Warnings 1) still appears.  --- Quote End ---   Fitter Ignored Assignments are usually the result of Altera IP setting some assignments in the (lower level) source. I assume it is the ALT_LVDS code responsible for the warning. I haven't used ALT_LVDS myself (as I wrote my own deserialiser handling 12 bits etc.) so I can't really give a good clue here.

[Altera_Forum]

Thank you josyb, 

 does your design handle 350 MHz DDR in speed grade 7 Cyclone III?  I already know that some people in this forum disadvice from using ALT_LVDS / ALT_LVDS_RX especially for odd factors. If i knew the use of constraints better, i would like to try writing my own deserializer.   Now timing is met only for the fast model. What does this mean in respect to the speed grade of the device? Is it right, that a speed grade C6 Cyclone won't be as slow as the "slow model"?  How can one constrain the timing analyze on C6 grades (varying only Temp and Volt), if slow always means C8 (Slowest speed grade in device density) and fast always means best voltage and temp conditions?

[Altera_Forum]

I would have to try, i used it in a CycloneII C6 at 300 MHz. I just tried that and got it running at 350MHz on a EP3C10F256C7 device, the C8 complains about the minimum clock width. 

 A C6 device is always faster then a C7 even at the 'slow' edge. That is the ultimate distinction. As on the 'fast' edge all speed grades may come close to each other. TimeQuest will properly constrain your design according to the speed grade specified. But if you can make it run for a C8 it will also run on a C7 or C6 speed grade.

[Altera_Forum]

Selecting the option "Register bitslip control input using rx_outclock" in Megafunction fixed the remaining critical warning 3) for both slow models. I don't understand why my own register was not sufficient. Do they use voodoo inside Megafunction? Maybe there are some multicycle constraints?