signal as loop termination condition

Altera_Forum · ‎01-09-2015

Hi all ;

I am writing vhdl at quartus ii 32 bit v. 13.1.0 web edition for terasic d0 board.

I am trying to write a time delay procedure but getting "VHDL Loop Statement error at <location>: loop must terminate within 10,000 iterations" (ID: 10536).

This is my main code.

library ieee;use ieee.std_logic_1164.all;
use work.time_issues.all;
entity DD is 
    port (clk:in std_logic);
end entity DD;
    
architecture behav of DD is
    constant step_count  : integer := 2500000; --#step's for 10ms at 50Mhz clk
    begin
    time_delay(clk,step_count);
end architecture behav;

And this is the package code.

library ieee;use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
PACKAGE time_issues IS
    PROCEDURE time_delay (signal t_clk:in std_logic; step_count: in integer);
END time_issues;
    
PACKAGE BODY time_issues IS
    PROCEDURE time_delay(signal t_clk:in std_logic; step_count: in integer) IS
    
        variable count : integer;
        variable count_out : integer;
    BEGIN
        count:=0;
        loop
            if (t_clk) then
                count := count + 1; 
            else
                count := count + 0; 
            end if;
            exit when (count = step_count);
        end loop;
        
        
    END PROCEDURE time_delay;
END PACKAGE BODY time_issues;

At the definition of error (ID: 10536) it is written that if i use a signal for loop termination conditon this may happen. But then if i want to synchronise my procedure with clk signal how would i do it.

I tried to use "wait until clk;" but appears to be i cannot use wait statement in a procedure.

Any help ? Thanks

Altera_Forum · ‎01-09-2015

Yes, this will never work. Loops unroll into hardware.

You need to think about the hardware you're trying to create, not the software style code. (Im guessing you're a programmer)

You need a counter in a synchronous process, and then finish when the counter reaches a certain value.

Another issue you have is that your design has no outputs. Then it actually does nothing on real hardware, and will synthesise to nothing (when you can get it to compile).

Altera_Forum · ‎01-09-2015

So there is no way to synchronise a procedure with clock signal. But what should i do then for a just 1 line code in order to achieve a time delay. Entity instantiation may be?

Altera_Forum · ‎01-09-2015

I think you need to stop. Take a step back.

Your code currently does nothing on a real FPGA, because it has no outputs. Therefore, it is useless for synthesis.

You can synchronise a procedure with a signal just fine. You can also use any wait statments you want in a procedure. But this is all for simulation. For synthesis you need to think about the logic you want to create, and then describe it. For synthesisable code you probably never want to use procedures.

You need a counter, in a synchronous process.


signal count : unsigned(10 downto 0);
process(clk)
begin
    if rising_edge(clk) then
        
        if count < SOME_NUMBER then
            count <= count + 1;
        end if;
        
        if count = SOME_NUMBER then
            --do something
        end if;
    end if;
end process;

Altera_Forum · ‎01-09-2015

Of course my design will have some outputs but in the begining i wanted to handle and finish that time delay issue. I'll take your sentence "For synthesisable code you probably never want to use procedures." as a guideline for synthesizable code.

Thanks a lot.

Altera_Forum · ‎01-09-2015

I highly recommend you find a good textbook or tutorial on digital logic design with VHDL

Altera_Forum · ‎01-13-2015

Hii guys how can I interface an ldr as input and an led as output to an FPGA (de2 board). Pls give me hints