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signaltap erroneous trigger

Altera_Forum
Honored Contributor II
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I have the trigger set for rising edge on a bidirectional FPGA pin. My oscilloscope does not indicate a trigger and the signal is constantly low, but signaltap is indicating a pulse is present.

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Altera_Forum
Honored Contributor II
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First, you should know that SignalTap doesn't really capture signal off this bidir pin directly. Opening the technology map viewer or resource property editor, you'll notice that what feeds the SignalTap logic is the input signal only. To include the output direction, you have to find the output driver and add that into SignalTap as well. Understanding this helps you correlating capture result between the scope and SignalTap. 

 

 

Second, SignalTap is latching in the core-level signal only. The signal is transformed from the pin-level signal based on the IO standard set in your project within the IO cell before reaching SignalTap. What you see in the waveform is the transformed result. I'd check two things: first, check whether the IO standard on that bidir pin is set correctly; second, check whether the trigger voltage level is set appropriately on your scope. 

 

 

If they still don't match, I'd send a pulse to bidir pin from the PLD core in the output direction and capture that in your scope to validate.
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