signed and unsigned no effect?

[Altera_Forum]

Hi, 

 Im using modelsim on something of what would be a lowpass filter code in my DSP experience. But modelsim does not produce a different output on this "signed" variable. Can I get this behavour from verilog?  module module (  input clock,  input [23:0] in,  output reg signed[23:0] out = 0  );

[Altera_Forum]

You dont show what you're actually doing. But varaibles are treated as unsigned unless you explicitly declare them signed. And then verilog behaviour means if you add two unsigned values you get an usigned result.

[Altera_Forum]

Had a fresh look at it, and it worked right away today. 

All the used variables had to be labeled as signed. Opposed to just the output register.