simulating mixed VHDL and Verilog code in ModelSim

[Altera_Forum]

i'm simulating a testbench which is written in system verilog language in addition to the testbench i have 5 modules thet some of them are written in VHDL and some in verilog language when i want to simulate it with modelsim and i run the testbench module , loading design error occurs and it says altera version supports only single HDL I want to ,is there any other versions which support simulating multiple languages? tnx a lot

[Altera_Forum]

Yes, the full licensed versions of Modelsim and Questa support multiple languages; SystemC, VHDL, SystemVerilog, etc. 

 But it ain't free ...  You can use Modelsim-ASE if you first use Quartus to output a Verilog netlist for your synthesizeable VHDL code. You can then run your SystemVerilog testbench with that code. You'll lose visibility into the internals of the design, but you can always run signals to I/O pins temporarily if needed ...  And hey, don't forget that you can always re-write your testbench in VHDL, or your code in SystemVerilog :)  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  Yes, the full licensed versions of Modelsim and Questa support multiple languages; SystemC, VHDL, SystemVerilog, etc.  But it ain't free ...  --- Quote End ---   Even the standard full license doesnt support it, you need a specific mixed language license. :(

[Altera_Forum]

--- Quote Start ---  Even the standard full license doesnt support it, you need a specific mixed language license. :(  --- Quote End ---    Oh, bummer. Thanks for the clarification. So let me re-phrase ...  The version of Modelsim/Questa you can access via Mentor Graphics' University Program allow mixed language simulations.  Cheers, Dave