Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
17267 Discussions

simulation error...

Altera_Forum
Honored Contributor II
‎09-27-2009 12:44 PM
1,547 Views

Error: Simulation results from J:/projects/uart_frq/db/uart_frq.sim.cvwf (0 ps to 20.0 ms) do not match expected results from vector source file J:/projects/uart_frq/uart_frq.vwf 

Error: Logic level(s) do not match expected level(s) 

Error: Logic level 0 does not match expected logic level X for node "cnt" at time 0 ps 

Error: Logic level 0 does not match expected logic level X for node "frqout" at time 0 ps 

Error: Quartus II Simulator was unsuccessful. 4 errors, 0 warnings 

Error: Peak virtual memory: 123 megabytes 

Error: Processing ended: Sun Sep 27 14:50:43 2009 

Error: Elapsed time: 00:02:23 

Error: Total CPU time (on all processors): 00:02:21 

 

can someone tell me what is wrong???
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎09-28-2009 06:48 AM
648 Views

You specified in the waveform file that you expected the "cnt" and "frqout" to be 'X' at the beginning of the simulation, which is not the case. You should change those to the real expected signals, or change them to "don't care"

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.