simulation from schematic file

[Altera_Forum]

Hello, 

 I test Quartus II 10.0 web edition (SP1) and the native link with Modelsim-Altera.  I created a counter in a vhdl file and integrated it in a schematic file (bdf) ; because i find that it is a more easier way to create electronic parallel systems. There is no problem or error with the compilation process  As it is write in the Quartus documentation, i transformed the graphic file in vhdl using the create hdl design file from current file menu.   I writed a vhdl file for the test bench, and the run simulation (menu tools/run eda simulation tools/ eda rtl simulation). The modelsim result is   # Loading std.standard# Loading ieee.std_logic_1164(body)# Loading work.test_commande(a_test)# ** Warning: (vsim-3473) Component instance "inst_com : commande" is not bound.  And the result is that the numerical outpout does not change.  I attach a zip with the different files:  

• Top-level file (commande .bdf) and converted one : commande .vhd 
• included file : compteur.vhd (which is converted to obtain a symbol file for the graphic file 
• bench-mark file : test_commande.vhd 
• the project file 

  Thanks for your help,  EON

[Altera_Forum]

before you run NativeLink, you should remove commande.bdf from the project files, and make sure that commande.vhd is in the file list. then run Analysis and Elaboration, then run NativeLink RTL Simulation 

 as it is now, Quartus has not generated a ModelSim .do script that includes your converted commande.vhd file. in order for it to do that you have to run Analysis and Elaboration with the converted .vhd file as the top level of the project (and the .bdf has to be removed to avoid naming conflicts)  you may opt to use 2 QII project revisions to switch between .bdf and .vhd in your file lists

[Altera_Forum]

you can tell by looking at the <>rtl_vhdl.do file, commande.vhd isn't in the vcom list: 

 vcom -93 -work work {---/TP1/compteur_commande_bdf/compteur.vhd} vcom -93 -work work {---/TP1/compteur_commande_bdf/test_commande.vhd}

[Altera_Forum]

Hello ThePancake,  

 I tried to replace the bdf file by the vhd translated one in the project, but it appears some problems with the data types :  In the compteur's file, the counter variable is defined as integer range. After the translation from bdf, the corresponding variable is defined as std_logic_vector, and i used the same data-type in the test bench file.  So in the errors given by ModelSim Altera is coherent with :# ** Failure: (vsim-3807) Types do not match between component and entity for port "n".# Time: 0 ps Iteration: 0 Instance: /test_commande/inst_com/b2v_inst1 File: D:/user/noel/Enseignement/Cours/archi_systeme/doc_etudiants/Quartus/TP1/compteur_commande_bdf/compteur.vhd Line: 13# Fatal error in Architecture a_compteur at D:/user/noel/Enseignement/Cours/archi_systeme/doc_etudiants/Quartus/TP1/compteur_commande_bdf/compteur.vhd line 30# while elaborating region: /test_commande/inst_com/b2v_inst1# Fatal error in Architecture a_compteur at D:/user/noel/Enseignement/Cours/archi_systeme/doc_etudiants/Quartus/TP1/compteur_commande_bdf/compteur.vhd line 30# while elaborating region: /test_commande/inst_com# Fatal error in Process line__36 at D:/user/noel/Enseignement/Cours/archi_systeme/doc_etudiants/Quartus/TP1/compteur_commande_bdf/test_commande.vhd line 36# while elaborating region: /test_commande  This is disappointing because simulating such systems was very easy in the previous version, but i'm steel new with this one, so ...   Thanks, for your help.  EON

[Altera_Forum]

i don't think .bdf will generate HDL that uses types other than std_logic_vector and std_logic. it might be easiest to use integers internally in the compteur, but port it out as std_logic_vector

[Altera_Forum]

Effectively, if the counter is modified in that sense, there is no problem with the simulation. But i am disappointed by the evolution of Quartus, it is not a good path towards greater simplicity and ease of use.  

 So, maybe we should wait for the next version ...  Thanks,  EON

[Altera_Forum]

i'm not sure that .bdf to HDL ever used more than std_logic and std_logic_vector. complex types (even integer) are easiest to "flatten" down in to std_logic and std_logic_vector. you can also see this in SOPC Builder where only std_logic and std_logic_vector are supported