speed up simulations in Modelsim

[Altera_Forum]

How Can I get modelsim to use 1ns for a time interval for simulation rather than something in the Pico second range? Are there any other methods for speeding up simulation? It takes 45 minuts to get to 1ms as of now and I need to look at the design later on but I do not have time to wait. I'm using v6.5 PE 

 Thanks

[Altera_Forum]

--- Quote Start ---  How Can I get modelsim to use 1ns for a time interval for simulation rather than something in the Pico second range? Are there any other methods for speeding up simulation? It takes 45 minuts to get to 1ms as of now and I need to look at the design later on but I do not have time to wait. I'm using v6.5 PE    --- Quote End ---  Verilog or VHDL?  vsim -t 1 ns ....  will set the timescale to 1ns. But for Verilog it might complain about the files themselves having timescales set.  Can you figure out what is taking so long?  Look at your code and think about how the simulator will run it. Can you optimize it? For example, is there needless calls to functions or tasks? (Needless in that a single call to a function or task can be used to initialize a constant, and then the simulation use that constant).  Cheers, Dave

[Altera_Forum]

are you using any Altera IP netlists (.vo/.vho)?

[Altera_Forum]

--- Quote Start ---  How Can I get modelsim to use 1ns for a time interval for simulation rather than something in the Pico second range? Are there any other methods for speeding up simulation? It takes 45 minuts to get to 1ms as of now and I need to look at the design later on but I do not have time to wait. I'm using v6.5 PE   Thanks  --- Quote End ---   The time resolution generally does not affect the wall clock simulation time much, it simply provides the desired accuracy of the measured time. The simulator is event based so if there is nothing going on between now and 1 ns or now and 1 sec it will take the same wall clock time to advance. The events get queued into a list of signals that change along with the time that they change.   However, changing the simulator's time resolution can have some not so good effects. If you set the simulator's time resolution to 10 ns then any delays shorter than 10 ns will be simulated in 0 ns so the following are equivalent:  a <= b after 5 ns; a <= b after 0 ns; a <= b;    If you're simulating a post-route netlist, then there will be a lot of signals changing creating a lot of events thus taking a lot of wall clock time.   If your design is somewhat independent of the actual clock frequency then you may be able to simulate it at a lower clock speed, say 1/10 of normal. This will work if what you're simulating is actually time based rather than clock cycle based...doesn't happen too often but sometimes it does, but it also usually requires baking that knowledge into the design by providing for some form of 'CLOCK_PERIOD' generic that can be used in the design for those things that really do need to measure time rather than clock ticks.   Lastly, find a faster computer with 3GB+ of memory usually helps.   To be more specific, you'll need to provide a bit more info about what you're trying to simulate to see about ways to improve things.   Kevin Jennings

[Altera_Forum]

--- Quote Start ---   Lastly, find a faster computer with 3GB+ of memory usually helps.    --- Quote End ---    Faster computer yes, extra RAM not so much. According to Mentor, the 64 bit version of modelsim runs slower than the 32 bit version.

[Altera_Forum]

Greetings 

 Greetings. Thanks for the responses. I am using VHDL.   I tried the  vsim -t 1 ns .... and bumped the simulation up to 100ps however modelsim did not like that one bit an threw this error at me  # ** Fatal: (SIGFPE) Floating point exception.# Time: 200 ns Iteration: 2 Process: /tb_top/vcs_wrap_inst/vcs_2_dcb_inst/dpa0_inst/altlvds_rx_component/stratixiii_pll/u4/line__10872 File: libs/libs/altera_mf.vhd# Fatal error in Process line__10872 at libs/libs/altera_mf.vhd line 11040# # HDL call sequence:# Stopped at libs/libs/altera_mf.vhd 11040 Process line__10872   perhaps it has something do do with the PLL's in this design.    I do not know what a Altera IP netlists is an unfortunatly could not expound upon that one.    I am using modelsim 6.5 PE and running it on a windows i7 2.7ghz laptop with 8gigs of RAM.    The deisgn, I didn't write. I am in the process of trying to figure out how it works and then modifying the clocks.    Hope this helps.... Thanks again for the help   Bill

[Altera_Forum]

to know if you're simulating any netlists, check the simulation .do file for .vo or .vho files 

 i don't think the PLL is causing the simulation to slow down that much

[Altera_Forum]

Hi, 

 check here: altera.com/support/kdb/solutions/rd10112011_242.html  (please add the w's in the address above. I have less than 5 posts and it doesn't let me post links)  I just had the same error. Since you simulate PLL you have to use ps. In my case, even if the error is gone the PLL still doesn't function right, its output is dead. Looks like a loong night, hehehe..  cheers g