Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
Success! Subscription added.
Success! Subscription removed.
Sorry, you must verify to complete this action. Please click the verification link in your email. You may re-send via your
profile.
Hello All, I am new to Altera and I am using Agilex to do some interesting stuff. Does any one know whether Quartus Prime 20.4 have ip core to do subtraction with embedded pipelines? I only see Multiply Adder Intel FPGA IP core inside it. What is the best way to do subtraction? Shall I write it in verilog explictly?
