symbol creation in quartus prime pro.

[mahender]

How to create symbol for verilog file in quartus prime pro and simulate it.

I am very new to this,please answer me.

Thanks in advance...!

[Alberto_R_Intel]

mahender, Thank you for posting in the Intel® Communities Support.

In reference to your inquiry, just to let you know, I just moved your thread to the proper support department. They will further assist you with this matter as soon as possible.

Regards,

Albert R.

Intel Customer Support Technician

[SyafieqS]

Hi Mahender,

Assuming you are using =>18.0 version, you cant do this in Pro. Creating a symbol file no longer available in Pro starting 18.0 as symbol files are not an industry standard format and had been removed. To work around this limitation, you can do this in Standard or Lite.

[mahender]

Hi @SyafieqS ,

                                     I am using 21.2 version,then how can i create ip for my own verilog code and simulate it.please help me with this.

Thanks in advance....!

[SyafieqS]

Hi Mahender,

Yes you can create your own IP. You might need to refer to below document on how to do that.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-platform-designer.pdf#page=91

[mahender]

Hi @SyafieqS,

                                   By using this pdf only i can able to create my own ip,and able to create block design.But how to simulate this block design using testbench like we do in xilinx by creating and instantiating the wrapper file in testbench.

Thanks in advance....!

[SyafieqS]

You can do that, might need to watch below tutorial on how to do the simulation

https://www.youtube.com/watch?v=eviC0jP90ZA

Also might need to look into below document for details if you re using other tools 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-tp-simulation.pdf

[mahender]

Hi @SyafieqS ,

                                  That video is so helpful and that i have used for ip simulation,but i am asking for block design.I have created block design using one or more ip's(interconnection),simulation can be done as per your previous answer but what i have to do to instantiate the block diagram in testbench(for ip after simulation instance code will be generated and that code i use in the testbench)..?how can i generate instace file for block design..i have block design file like this...

[SyafieqS]

Hi Mahender,

For BDF, file I dont think Quartus have feature that can generate instance code for module instantiation unlike in qsys,might need to write your own. In 19.2 the most, you can simulate bdf easily with testbench generated automatically by toggling the input manually from file-> new file-> university program. If you intend to use Modelsim only simulate HDL, thus you probably need to convert those bdf to HDL, which those feature only available in Lite/Std.