synthesis instability

[Altera_Forum]

How is possible that the same design, synthetized different times without errors, sometimes on the FPGA correctly run and sometimes no its completly locked? What could be the possible causes? I'm using a stratix2 with quartus 6.0. There are particular structures that quartus cannot synthetized? Thanks a lot!:o

[Altera_Forum]

It might not be synthesis issues. I have seen this symptom when I have not covered everything in timing closure. Just last week I thought perhaps Quartus was messing up with my state machine, because it had two different states active at the same time. It ended up being the reference clock not staying locked. Reliance on signals across clock boundaries without proper clock domain bridging is another pot-hole that has caused inexplicable symptoms. Not since 2000 have I seen problems I could track back to a synthesis bug. 

 If it is a synthesis bug, you can prove it with timed netlist simulation or analysis of post mapped netlist.

[Altera_Forum]

It's a quite complicated design, that I don't know very well because someone else has written it, then perhaps could be than the timing it's not perfectly controlled. But Have I to set the constraints for every clock even if generated from the master one? It's the first time I work on FPGA, normaly I work on ASICs and I don't know very well how making timing constraints!

[Altera_Forum]

If you and your company has ASIC experience, and you are reviewing timing constraints, the SDC format option for Altera would make more sense for your application. There is plenty of documentation. I'd recommend timing closure first, then discovering more detail about what is not working by using Signal Tap next. Then you will have a better handle on what you are chasing. Best wishes - Randall

[Altera_Forum]

I agree, if you timing report does not meet he requirements (fmax, hold), 

the behavior can be random.  As a quick test, just cooldown the fpga with a freezer spray. If the design runs stable, this is a timing issue.

[Altera_Forum]

You also want to make sure that do not have any asynchronous logic in your design. That would cause the condition erratic behavior from route to route. You can check your timing report file for warnings of this nature. 

 Stan

[Altera_Forum]

"Processing --> Start --> Start Design Assistant" will run some checks for asynchronous paths.

[Altera_Forum]

Hello, 

 there is another possibility why the implementation doesn't work in different fits. If the design has different clock domains, take sure, that the signals are synchronized in a correct way. If the clocks are completly unrelated quartus cuts all timing calculations accross the clock boundaries. (Unrelated means, that the clocks are used or derived from different clock input pins.) So if the signals are not synchronized in a correct way, different parts of the logic can get different signal levels of the same signal in the new clock domain.

[Altera_Forum]

I have lunched The design Assistant there are some critical warning but none about asynchronous path. The problem is that I have different clocks obtain from a master by divider, gating and so on and so for... and the master clock could be programmed... it's difficult to make good timing constraints. Timing analyzer give me some hold time negative. It means that is not respected, isn't it? But if I set fmax is not sufficient?

[Altera_Forum]

Hi, 

 if you have a programable clock, constrain the design to the worst case. (This would be in the most cases the maximum frequenze which can be set. FPGAs normaly can't reache the frequenze as high as ASICs can do. To the timing violations: Where do they happen? Are the violations from pins or across clock boundaries? If the violations happen at io pins, than take sure that the registers in the pins are used. If the violation happens accross clock boundaries there might be a synchronization problem. In normal case different clock domains are unrelated. However Quartus takes all clocks driven from one clock pin (also through a pll) as related. For this clocks it calculates a needed register to register delay which can be very few (1 ns or less). If the hold violations happen in the same clock domain, there is a chapter in the quartus II handbook about optimizations.

[Altera_Forum]

--- Quote Start ---  I have different clocks obtain from a master by divider, gating and so on and so for... and the master clock could be programmed... it's difficult to make good timing constraints. Timing analyzer give me some hold time negative.  --- Quote End ---     It sounds like you are dividing and gating with logic. It is highly preferred that dividing be done with a PLL or clock enable and that gating be done with a clock control block (a dedicated silicon resource available in some device families) or clock enable. Having logic resources (either registers for dividing or LUTs for gating) or even nonglobal routing in the clock path introduces skew if the source and destination register don't have the same clock path (crossing to or from a divided/gated clock domain or between registers in the same domain with nonglobal routing). This clock skew can cause either the clock hold violations you mentioned or clock setup violations.  If you are using the Classic Timing Analyzer, right clock one of the failures in the Clock Hold (or Clock Setup) table and select "List Paths". In the Messages window System tab, press the <Ctrl> key while clicking the plus sign at the left end of the new message to expand everything at once (or just keep clicking plus signs to expand one step at a time). Look at what is happening in the requirement section. Pay particular attention to what is in the clock skew section. Your logic for dividing and gating should be shown in the clock skew section.  I've made other comments about this in "Altera Forums > Tools Related > Quartus II Discussion > PLL Clock Frequency" (http://www.alteraforum.com/forum/showthread.php?p=1273#post1273). That post has a suggestion to do the dividing with a clock enable (as good as using a PLL, but might require more changes to your source files because you didn't use a clock enable from the beginning) and suggestions in case you do continue to drive your clocks with logic resources.

[Altera_Forum]

I'm trying to change the design and to make a good timing constraints following this made for the ASIC as you have suggested me. I will tell you the results! Thank you to every one! :-)

[Altera_Forum]

It seems that now the synthesis is ok. I have substitueted the gating and the mux clock with the block control block and set as timing constraints fmax: now all seems working! Thank you very much to all of you!:)