_tb has no architecture (error in modelsim(of altera)(14.0)), plz help

[Altera_Forum]

simple program and its testbench(copy from book of volnei a. pedroni 2 e) 

---------------- LIBRARY ieee; USE ieee.std_logic_1164.all; ------------------ ENTITY mydesign_tb IS END ENTITY; -------------------------- ARCHITECTURE testbench OF mydesign_tb IS  ---DUT declaration:------  COMPONENT mydesign IS  PORT (clk, rst, din: IN STD_LOGIC;  dout: OUT STD_LOGIC);  END COMPONENT;  ----signal declarations:-----  SIGNAL clk: STD_LOGIC := '0';  SIGNAL rst: STD_LOGIC := '1';  SIGNAL din: STD_LOGIC := '0';  BEGIN  ---DUT instantiation:-----  dut: mydesign PORT MAP (clk, rst, din, dout);  ----stimuli generation:-----  clk <= NOT clk AFTER 40ns;  rst <= '0' AFTER 80ns;  din <= '1' AFTER 160ns, '0' AFTER  240ns, '1' AFTER 32ns;  END ARCHITECTURE;  ----------------------- --------------------------------------------------------------------------------------------------  LIBRARY ieee; USE ieee.std_logic_1164.all; -------------------- ENTITY mydesign IS  PORT (clk, rst, din: IN STD_LOGIC;  dout: OUT STD_LOGIC); END ENTITY; ---------------------- ARCHITECTURE mydesign OF mydesign IS  BEGIN  PROCESS (clk, rst)  VARIABLE q: STD_LOGIC_VECTOR(0 TO 3);  BEGIN  IF (rst='1') THEN  q := (OTHERS => '0');  ELSIF (clk'EVENT AND clk='1') THEN  q := din & q(0 TO 2);  END IF;  dout <= q(3);  END PROCESS; END ARCHITECTURE; ------------------------------ but when I try to compile(both, error on tb-"unknown identifier dout") and simulate tb, error about no architecture of tb on my altera modelsim 14.0 on linux-ubuntu 14.04. plz help, eric

[Altera_Forum]

you need to declare dout in the testbench declaration area like din...

[Altera_Forum]

thanks your reply/suggestion, I follow / tried, the result is : although it compile and simulate(tb), but no wave form and its message stated: no data(for all variables, clk, rst, din, dout), so plz help again or any other advanced programer's advice. thanks a lot in advance. (according to that book, "circuit design and simulation with VHDL 2nd edition, that example is worked on MentorGraphic's modelsim, not altera's; so 

if anyone have successful run's altera modelsim program(both design file and its testbench file in vhdl(.vhd) form of short/simple programs, plz point/refer a link or post on this thread. thanks)

[Altera_Forum]

--- Quote Start ---  thanks your reply/suggestion, I follow / tried, the result is : although it compile and simulate(tb), but no wave form and its message stated: no data(for all variables, clk, rst, din, dout), so plz help again or any other advanced programer's advice. thanks a lot in advance. (according to that book, "circuit design and simulation with VHDL 2nd edition, that example is worked on MentorGraphic's modelsim, not altera's; so if anyone have successful run's altera modelsim program(both design file and its testbench file in vhdl(.vhd) form of short/simple programs, plz point/refer a link or post on this thread. thanks)  --- Quote End ---    after simulation you will need to add these objects (clk,reset,din,dout) to ayour waveform. then run the waveform.