tco question on VHDL

Altera_Forum · ‎09-19-2009

I've this VHDL code:


ENTITY count_tia IS
    PORT
    (
        clock:         IN STD_LOGIC;
        sload:         IN STD_LOGIC;
        data:         IN integer RANGE 0 TO 127;
        result:        OUT integer RANGE 0 TO 127
    );
END count_tia;
ARCHITECTURE rtl OF count_tia IS
    SIGNAL result_reg : integer RANGE 0 TO 127;
BEGIN
    PROCESS (clock)
    BEGIN
        IF (clock'event AND clock = '1') THEN
            IF (sload = '1') THEN
                result_reg <= data;
            ELSE
                result_reg <= result_reg + 1;
            END IF;
        END IF;
    END PROCESS;
    result <= result_reg after 100ns;
END rtl;

The classical timer analyzer say that the maximum tco (between clock and result) is 5ns, but this is not possibile because there's a delay time greater than 5ns.

What's wrong?

Altera_Forum · ‎09-19-2009

Because the "after 100ns" doesn't synthesize to anything.

Altera_Forum · ‎09-19-2009

--- Quote Start ---

Because the "after 100ns" doesn't synthesize to anything.

--- Quote End ---

what can i do to produce a delay?

My clock is 25Mhz and i want to creare a delay about 10ns, i cannot use the clock to produce a signal delay...

Altera_Forum · ‎09-19-2009

Well I'm just a hobbyist so take my advice with a grain of salt, but I've understood that generating useless logic to achieve a delay is just asking for troube. You have to know the architecture well and even if you get it right, it will still be technology dependent (synthesizing for some other device will likely produce different results).

What you could do is still make it synchronous. If the device you're targeting has PLLs, you could use one to generate a 100MHz clock inside the device. Then you could use that 100MHz clock to clock a register that would create a 10ns delay.

You should of course take into account that the I/O buffers of the device will have delays of their own (and you should probably synchronize the input signals if they're asynchronous to the clock).

Altera_Forum · ‎09-19-2009

Elpuri had already answered well. I will add this:

You don't mean Tco really. Tco is the clock edge to output transition time for a given register.

You probably mean one clock latency needed, so just add one more register at the output as follows:


ENTITY count_tia IS
    PORT
    (
        clock:         IN STD_LOGIC;
        sload:         IN STD_LOGIC;
        data:         IN integer RANGE 0 TO 127;
        result:        OUT integer RANGE 0 TO 127
    );
END count_tia;
 
ARCHITECTURE rtl OF count_tia IS
    SIGNAL result_reg : integer RANGE 0 TO 127;
BEGIN
    PROCESS (clock)
    BEGIN
        IF (clock'event AND clock = '1') THEN
 
            IF (sload = '1') THEN
                result_reg <= data;
            ELSE
                result_reg <= result_reg + 1;
            END IF;
 
            result <= result_reg;
 
        END IF;
    END PROCESS;
 
END rtl;

Altera_Forum · ‎09-20-2009

Understood. Thank you!