testbench simulation

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Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

testbench simulation

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i have written a project which compiles in quartus II giving the RTL output correct

i am using Modelsim for simulation and have written a testbench

for simulation i give the data through testbech which is 53 bytes

it requires look up table data to be initialized in the Rom , i have created a .mem files to initialize and kept the file in the project folder

when i run the simulations and view the memory content it shows all zeros and also look up table Rom uninitialized

what could be the problem ? or am i not following the simulation steps correctly.can you please tell me the steps of simulation..

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