the throughput of ddr2 decrease after adding a pipeline bridge！

[Altera_Forum]

Hi, 

 Has anyone ever met the case that the throughput of ddr2 decrease severely after adding a pipeline bridge between the master and the ddr2 controller?    As you can see from the attached picture, My SOPC system is very simple. The difference between the two system is one contains a pipeline bridge between the two master and the ddr2 controller, while the other not.    Also i have attached a second picture containing the signals that grabbed by SignalTap. Obviously the ddr2 controller launches read request more frequently for the system containing no pipeline bridge, though the master behaves the same for the two system.   The decrease on the throughput of ddr2 controller is not acceptable for my project. Does anyone have a method to fix the problem? or it's just the normal phenomenon.   One more question, in my SOPC system, 7 dma masters would access the ddr2 controller simultaneously. while after connecting the masters to the controller directly, critical paths appeared in the ddr2 arbitration module. Can anyone give some advice on how to increase the fmax of the SOPC system?   Thanks for your reply!

[Altera_Forum]

No you shouldn't loose a lot of bandwidth, especially with bursts and pipelined transfers. Double click on the pipeline bridge and check that "allow bursts" is enabled. Set the burst size to the required value (at least same size as the master). 

Check also that you are using the exact same clock on the pipeline bridge and the masters/slaves it is connected to. Clock crossing mechanisms can also reduce latency.  You are on the right track, adding pipeline bridges is the best way to increase your system Fmax, especially with so many masters connected to one slave. Adding another pipeline bridge between the CPU's data/instruction masters and its jtag_debug_module also helps.

[Altera_Forum]

Hi, 

 Thanks for your reply!   I have checked the setting of the pipeline bridge. Everything seems to be what you said. I have enable the burst option, and tried burst size of 8,16,32, while no improvment occured! As to the clock, only one clock exited in the SOPC system, so it won't be wrong!   In my SOPC system, two avalon master would access to the ddr2 controller, that's nios processor and vga module. It's a pretty simple design.   I have attached my quartus project below, would you please be so kind to download the design and check for me？   I have also saved a picture may be useful in the root directory as "timming.bmp", which containing the signals i grabbed by signaltap.

[Altera_Forum]

I'm sorry, I can't see what's wrong then... Can you monitor the 'burstcount' signal before and after the bridge? To see if it is really the bridge that stops the bursts...