three stages for a shifter (shifting by 0~7 bits)

[Altera_Forum]

Is there a way to implement a shifter (shifting by 0~7 bits) solely based on combinational logic? If it is a 3-stage shifter, the output of the previous shifter will be further shifted by all the shifters after it, one by one. Without using clock, can we do it in Verilog?

[Altera_Forum]

You can.. But what are you looking to do? 

 assign output_c = input_r >>> shift_amount_r;  works

[Altera_Forum]

A combinational shifter isn't but a multiplexer for each bit. Synthesis-wise, it's meaningless if you describe it as single- or multistage in your behavioral or structural code. The synthesis tool will chose an optimal implementation of the x8 multiplexers without your help.

[Altera_Forum]

If you want a logical shift it's << and >> by a non-constant. For arithmetic shifts like anakha said use >>> and <<< by a non-constant. 

 Since you are not using a pipelined shifter there is no point describing the shifting operation in multiple stages since the built in operator will implement something more optimized (if you hand coded multiple stages Quartus would restructure it anyway)

[Altera_Forum]

I think we need to define what shift we are talking about.  

arithmatic bit shifting on a data bus can be done without the clock and it is just matter of moving bits to new locations in the bus. time shifting on the other hand requires memory i.e. registers or ram to move samples relative in time.  It sounds like the original post is about arithmatic shifting.