timeQuest help

[Altera_Forum]

Hi there, 

 I want to use timeQuest to find the max frequency of my design. I never used this tool before, and it's hard for me to get start.  I'm trying to write the sdc file myself, but meet the problem at the very start. I use this command  create_clock -name clk_in -period 40 -waveform {0 20} [get_ports clk_1]  clk_1 is the input in my verilog code, why the timeQuest shows the warning Warning: Ignored filter: clk could not be matched with a port Warning: Ignored create_clock: Argument <targets> is an empty collection  Can someone give me a example including the verilog design file and sdc file? Thanks for your help

[Altera_Forum]

--- Quote Start ---  Hi there,  I want to use timeQuest to find the max frequency of my design. I never used this tool before, and it's hard for me to get start.  I'm trying to write the sdc file myself, but meet the problem at the very start. I use this command  create_clock -name clk_in -period 40 -waveform {0 20} [get_ports clk_1]  clk_1 is the input in my verilog code, why the timeQuest shows the warning Warning: Ignored filter: clk could not be matched with a port Warning: Ignored create_clock: Argument <targets> is an empty collection  Can someone give me a example including the verilog design file and sdc file? Thanks for your help  --- Quote End ---    The warning says clk(it does not say clk_1) check your sdc statement and make sure the correct file is used

[Altera_Forum]

--- Quote Start ---  The warning says clk(it does not say clk_1) check your sdc statement and make sure the correct file is used  --- Quote End ---   thanks&#65292;I examined the code found that all the logic are combinational logic, which doesn't use clk_1. I think the software‘s optimization omitted clk in compilation.  Now my problem becomes how to find out a pure combinational logic design's delay? In other words, I want to find out how fast the Input changing would not lead the output error. thanks a lot

[Altera_Forum]

--- Quote Start ---  thanks&#65292;I examined the code found that all the logic are combinational logic, which doesn't use clk_1. I think the software‘s optimization omitted clk in compilation.  Now my problem becomes how to find out a pure combinational logic design's delay? In other words, I want to find out how fast the Input changing would not lead the output error. thanks a lot  --- Quote End ---    Your new problem is by itself a problem hard to understand. You better use clock on your logic as FPGAs are meant to unless you are after some small combinatorial design in which case you need to tell more about your input/output logic

[Altera_Forum]

--- Quote Start ---  Your new problem is by itself a problem hard to understand. You better use clock on your logic as FPGAs are meant to unless you are after some small combinatorial design in which case you need to tell more about your input/output logic  --- Quote End ---     https://www.alteraforum.com/forum/attachment.php?attachmentid=8465 Hi kaz, thank you for replying. I mean my design only has the comb part, I want to know the delay of this part. For example when the signal comes to the data_in, how long does it take to get through the comb part then comes out from the data_out.

[Altera_Forum]

so you got clock now and the comb section is happy in between. So don't worry about path delay as the compiler will tell you. just enter clock speed.