Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
17268 Discussions

timequest warning

Altera_Forum
Honored Contributor II
‎05-13-2010 03:16 AM
1,028 Views

I build a nios cpu in my project. The SOPC generate a file named "cpu.sdc ". In this file there is a statement : "set_false_path -from [get_keepers *$cpu_oci_debug_path|monitor_ready] -to [get_keepers *$cpu_jtag_tck_path|monitor_ready_sync1]". 

When I use Timequest Timing Analyzer , there's waring message : "*cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|monitor_ready_sync1 could not be matched with a keeper." 

How can I do to resolve this message waring?
0 Kudos

Link Copied

0 Replies
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.