timing simulation in modelsim after quartus place and route

[Altera_Forum]

Hi, 

 I wrote a simple RAM in deffernt versions. I get data and address and my output is the address and the data after place and route and running timing simulation (checked at least 10 different versions) I never get my signals synchronized to the clk (rising_edge)  for example:  entity sobel_ram_start_double_process is   generic(add_width: integer:= 2;data_width: integer:= 4);  port ( clk : in std_logic;  wr_en : in std_logic;  data_in : in std_logic_vector (data_width-1 downto 0);  address : in std_logic_vector (add_width-1 downto 0);  address_ram1 : out std_logic_vector (add_width-1 downto 0);   data_out : out std_logic_vector (data_width-1 downto 0)); end entity;  architecture sobel_ram_start_double_process_arch of sobel_ram_start_double_process is  type mem is array (2**add_width-1 downto 0) of std_logic_vector(data_width-1 downto 0);  signal array_data : mem;  signal address_save : std_logic_vector(add_width-1 downto 0);   begin  getting_data:process(clk)  begin   if rising_edge(clk) then  if wr_en='1' then  array_data(conv_integer(address))<=data_in;  end if;  end if;   end process;     address_saving:process(clk)  begin   if rising_edge(clk) then  if wr_en='1' then  address_save<=address;  address_ram1<=address_save;  end if;  end if;   end process;   end architecture;   In modelsim it works perfect but after using *.vho and *.sdo I dont understand what the quartus does!!!  address_ram1 gets a value without my initialization... instead of simple pipeline implementation the data is presented in strange way... I tried almost every version (2 process, 1 process, outside the process) and couldn't synchronize my signals (address_ram1 and the output) the the clk :-( even under the same wr_en I get the data with delay (and not the delta)...  What should I do?  Tenx  ari

[Altera_Forum]

I cannot answer your question, but fell into a big laugh, when elaborating your code: Have a look a the wunderfull smilies interrupting the process name - somehow cute .. :)

[Altera_Forum]

hello, 

 I want to run an EDA gate level simulation to my VHDL design using QuartusII 6.1 and Altera Modelsim 6.1g but when i run the simulation I obtain this error:  ** warning: (vsim-3473) component instance "soc : mapping_minimips" is not bound. # time: 0 ps iteration: 0 region: /test_mm file: d:/these/inria/fpga_2s180/vga/4pe_avecvga/avec_xnet_and_linear/test_mm.vhd # ** fatal: sdf files require altera primitive library # time: 0 ps iteration: 0 instance: /test_mm file: d:/these/inria/fpga_2s180/vga/4pe_avecvga/avec_xnet_and_linear/test_mm.vhd line: unknown # fatal error while loading design # error loading design # error: error loading design  # pausing macro execution  # macro ./standard_run_msim_gate_vhdl.do paused at line 12    Could you please help me, thanks in advance  Mouna.

[Altera_Forum]

I think you are simulating with modelsim at RTL level. i.e. with no routing delays eveything switches in zero time. All signals change on clock edges. 

 If you are using the vho file in the Quartus simulator then this is a gate level netlist and includes all the timings post synthesis (Actually the timing info is also in the sdo). If you like this is real timings with real delays through RAMS etc.  Hence RAM output signals etc will be delayed until after the clock edge. This is your RAM latency.  Hope this helps

[Altera_Forum]

Ari 

 I can't see where your code assigns data_out, so i can't advise on why it's not synchronised.  When the real logic and routing delays are included in your simulation, you will see signals changing a short time after the clock edge (essentially you can regard your RTL simulation as having the logic and routing delays reduced to zero). Is that all that you are seeing or are your outputs completely unsynchronised?  Mouna  It looks like you don't have all of the libraries that you need. Look in the library list and check that the necessary Altera libraries are there - if not add them in.

[Altera_Forum]

When analyzing ModelSim error reports, start at the first error. The other may be just follow-ups. xxx is not bound = missing design file or library is always sufficient to cause simulation failure.