too many sdc constraints?

[Altera_Forum]

Is there such a thing as too many sdc constraints. I ended up producing over 2000 multicycle 

and false path constraints. my design fills a stratix V to 70%. And my main system clock is around 200MHz. I wanted to know if quartus execution time will suffer due this. I will kick off a run to find out but wanted to get a heads up from anyone whos been there.

[Altera_Forum]

I've seen that many and haven't heard of it being a problem. It might increase run-time a little, but should be small overall. The biggest concern is managing/verifying them. If the design changes, etc., it can be difficult. I try to wildcard in order to reduce the number of assignments so I can mentally keep track of them. The downside is the danger of capturing something you don't want MC'd, so it's a trade-off.

[Altera_Forum]

2000 Exceptions can have a big impact to run time if TimeQuest cannot merge them while processing them. It is therefore recommended that you try to use groups and wildcards to reduce the number of lines. Even if TimeQuest can do this fast, you are still making it work harder. 

 For example, can you use something like  set_false_path -from { foo* bar* *foobar* } -to { ab* }  instead of  set_false_path -from { foo1 } -to { ab1 } set_false_path -from { foo2 } -to { ab1 } etc.

[Altera_Forum]

thanks all!