tree structure

Altera_Forum · ‎02-25-2014

hii

pls give an idea to implement a verilog code to construct a tree structure.Also an array reusing idea.because we need to reduce the array size each time.

Altera_Forum · ‎02-26-2014

This is far too few information.

What exactly do you need? Do you want to create a Top-Entity which holds one or more Objects of your Verilog-Code? I think for beginners it would be a good start to create a Symbol-File of your code and place it in a Schematic-File (*.bdf). Then you can actually "see" what you have programmed.

What array? How do you want to reduce the array size? Hmmm, if I ask my crystal-ball I think you want to create some instances of a Verilog-Thingy holding an array, and every instance should hold an array of different size.

If this is the case try using "generics" in your code.

Altera_Forum · ‎03-16-2014

Hello, I suggest this code:


module NodeType (  );
endmodule
module TreeTemplate (  );
 
parameter TREE_LEVEL= 4;
NodeType node();	
generate
if ( TREE_LEVEL >0 )
begin
	TreeTemplate# ( TREE_LEVEL-1 ) leftSubtree (  );
	TreeTemplate# ( TREE_LEVEL-1 ) rightSubtree (  );
end
endgenerate
endmodule

I have used this principle in the implementation of sorting module. It was pleasant surprise, that one can make recursive modules in verilog.