use of # in verilog declaration

[Altera_Forum]

Hi All, 

 What does# mean within the context of verilog module declarations ?  Thanks,  mark  ================  module zl_fifo_2#  (  parameter Width = 0 ) (  input clk,  input rst_n,  //  input data_in_req,  output data_in_ack,  input [Width-1:0] data_in,  //  output data_out_req,  input data_out_ack,  output [Width-1:0] data_out );

[Altera_Forum]

# means generic definitions or generic map. Its a region where you can define a load of parameters that can be modified when the module is instantiated.