(vcom-1105) Name (indexed name) does not denote an entity name.

[RogerJL]

Hi,

Finally tracked down why I get this from modelsim-altera when using 

Run Simulation Tool -> RTL Simulation

The generated PROJECT_run_msim_rtl_vhdl.do is not generated in correct order

file: cnf_regs_meas.vhd

ENTITY cnf_regs_meas IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT (...);

END cnf_regs_meas;

ARCHITECTURE cnf_regs_meas_architecture OF cnf_regs_meas IS

COMPONENT cnf_regs IS
GENERIC (...); PORT (...);

FOR REGS : cnf_regs USE ENTITY work.cnf_regs_generic(cnf_regs_generic_architecture);

BEGIN

END cnf_regs_meas_architecture;

file: cnf_regs_generic.vhd

ENTITY cnf_regs_generic IS

  GENERIC (...)

  PORT (...)

END cnf_regs_generic;

ARCHITECTURE cnf_regs_generic_architecture OF cnf_regs_generic IS

PROCESS ...

BEGIN

  - - -

END PROCESS;

END cnf_regs_generic_architecture;

Problem is that PROJECT_run_msim_rtl_vhdl.do gets generated as, when cnf_regs_meas is compiled the required cnf_regs_generic does not exist in work.

- - -

vcom -2008 -work work {.../cnf_regs_meas.vhd}
vcom -2008 -work work {.../cnf_regs_generic.vhd}

- - -

Solution: swap compile order of these two files

Is there any other way?

[Nurina]

Hi,

By swapping the compile order, do you mean editing the .do file thus using a scripted simulation flow instead of NativeLink? If so, I do think that's the only workaround for your problem unfortunately.

Regards,

Nurina

[Nurina]

Hi,

We did not receive any response to the previous question/reply/answer that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

Regards,
Nurina

PS: If you find any comment from the community or Intel Support to be helpful, feel free to give Kudos.

[RogerJL]

Yes, swap the compile order of the two files.

This issue with a simple work around took me hours, checked every setting I could find...

It just did not cross my mind that the tools did not generate compiling code.

I would really like to be able to use NativeLink, especially important as when I am done with my editions someone else might pick this project up and expect NativeLink to work out of the box - repeating my mistakes...

[Nurina]

Hi,

I can raise this issue to engineering and see if they can do anything about it.

Can you let me know which version of Quartus you're using and which device you're synthesizing the code on?

Thanks!

Best regards,

Nurina

[Nurina]

Also, can you attach your qar file? To do this, go to Project->Archive Project

Best regards,

Nurina

[Nurina]

Hi,

We did not receive any response to the previous question/reply/answer that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

Regards,

Nurina