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New Contributor I
54 Views

verilog data latching.

Hi.

can anybody help to how to latch the data with different clock  inputs  (means: i'am getting an 12 bit data serially at 200Mhz clk input. i'm storing it in reg varialble, and i want use that 12bit data in 50Mhz clock source in another module).

Thanks.

regards

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Moderator
47 Views

you may use set multi cycle clock for this type of requirement. You can refer to https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/analyze/sta/sta_db_set_multicy...


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Moderator
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We do not receive any response from you to the previous answer that we have provided. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 


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New Contributor I
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Thank you so much sir. i'm done with the task. 

Thanks for valuable feedback

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