verilog 'default' value in quartus throws Err10818

Altera_Forum · ‎09-30-2010

Hi all,

yesterday I got a problem while adapting an foreign project in verilog for my testboard. The code includes a lot of lines where a kind of default value has been defined and quartus always throws an error 10818 saying that it is not able to synthesise this code.

The code always follows the following pattern:


always @(posedge ...)
aout <= 0;
if (...) begin
   if (...) begin
      if (...) begin
         aout <= 1;
      end
      else begin
         ...
      end
      ...
   end
   ...
end

My experience is very limited, but I think that this code is not following the code style guidelines, although modelsim and an actel compiler seem to tolerate this code. It would be a lot of work to assign 'aout' in all "else" cases and I am sure I would miss one.

ok, but is there any way to define a kind of 'default' value, for all if-branches, where 'aout' is not assigned that is following the code style guidelines ?

thanks for your help.

any hints for documentation about this pattern are welcome.

cheers, eag1e

Altera_Forum · ‎09-30-2010

This code is badly written.

If you don't have time to rewrite it completely i can give a suggestion.

What if you create two procedural blocks?

One should generate the "aout" signal in a combinatorial way and hence is not synchronized by the clock.

The second one is a simple flip flop that synchronizes the signal.

Maybe that in this way the synthesizer has a simplified life.

Altera_Forum · ‎09-30-2010

Thanks nplttr for your suggestion,

probably this will be the best way.

The whole structure is difficult to understand because I think it's written far to complicated.

It just seemed that I found the real reason for the quartus-error and I have to say, I have hidden the most important part:


always @(posedge wb_rst_i)
aout <= 0;
if (wb_rst_i) begin
   if (...) begin
      if (...) begin
         aout <= 1;
      end
      else begin
         ...
      end
      ...
   end
   ...
end
elseif (...) begin
...
   aout <= 1;
...
end

So I think the main problem quartus has, is that there are both clock edges used due to the 'elseif' in the end.

But why the hell, is it synthesisable when I comment out the first 'aout <= 0' ?

Altera_Forum · ‎09-30-2010

The code doesn't look like a double edge triggered (that is however not synthesizable).

You only have the posedge wb_rst_i in the sensitivity list (for a double edge you should have "posedge ... or negedge ...").

Did you try as I said?

My idea is:

always @(every signal on the right side of the assignments) aout_comb <= 0; if (wb_rst_i) begin if (...) begin if (...) begin aout <= 1; end else begin ... end ... end ... end elseif (...) begin ... aout_comb <= 1; ... end

always @(posedge wb_rst_i)

begin

aout <= aout_comb;

end

Altera_Forum · ‎09-30-2010

hmm, bad - you're right.

Time to go for a walk - I seem to have tomatoes on my eyes.

No sry, I didn't try it yet, because it's not only aout, there are 7 registers in a really huge if-else-tree, that cannot be infered.

I'm just on my way to split it like you said - its a lot of work - but nobody told me that a wishbone-controller would be easy.

thanks :)

Altera_Forum · ‎10-01-2010

Hello again,

quartus is going to drive me crazy.

at first nplttr, no - it didn't work.

So I tried to write the controller for my own memory bus first and earned the same:

--- Quote Start ---

Error (10818): Can't infer register for "fb_data[0]" at SD_controller_FlexBus.vhd(26) because it does not hold its value outside the clock edge

--- Quote End ---

for

LIBRARY ieee;
USE ieee.std_logic_1164.all;
    
ENTITY SD_CONTROLLER_FB IS
    GENERIC( BUSWIDTH: natural := 8);
    PORT
    (
        fb_data                                : inout std_logic_vector(7 downto 0);
        fb_addr                                : in std_logic_vector(19 downto 0);
        fb_cs                                    : in std_logic_vector(1 downto 0);
        fb_oe                                    : in std_logic;
        fb_rw                                    : in std_logic;
        fb_ale                                : in std_logic;
        
        clk                                    : in std_logic;
    
        fb_rx_bd                                : out std_logic_vector(BUSWIDTH-1 downto 0);
        fb_tx_bd                                : in std_logic_vector(BUSWIDTH-1 downto 0)
   );
END SD_CONTROLLER_FB;
ARCHITECTURE SD_CONTROLLER_FB_architecture OF SD_CONTROLLER_FB IS
BEGIN
        PROCESS (fb_ale)
        BEGIN
                IF (rising_edge(fb_ale)) THEN
                    fb_data <= "ZZZZZZZZ";
                ELSE
                    fb_data <= "11111111";
                END IF;
        END PROCESS;
END SD_CONTROLLER_FB_architecture;

WHY ? there are 2 damn constants for now ?!

At this stage its so easy that I would be able to solder this circuit.

cheers, eag1e

Altera_Forum · ‎10-01-2010

ok,

http

www<dot>altera<dot>com/support/examples/vhdl/v_bidir.html

does not work - also an Error 10818.

The examples seem to be for a PLD.

Is it a FPGA-specific problem???

Altera_Forum · ‎10-04-2010

You should stick to the standard process model to be sure it can be synthesized:

  process (clock,reset)
  begin
    if (reset='1') then
      -- reset condtions
    elsif rising_edge(clock) then
      -- clocked actions
    end if;
  end process;

Don't try to do anything on the falling edge of the clock in the same process.