Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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verilog define in the .qsf or .tcl for quartus?

AEsqu
Novice
768 Views

Hello,

 

I use this command in a Synplify project to define for a verilog check code translation:

 

set_option -hdl_define -set {"WITH_TH"}

 

This is then picked in verilog:

`ifdef WITH_TH

  code line here will be picked

`endif

endmodule 

 

My question:

How to do it for Quartus?

I'm used to the 

set_parameter -name ...

but that is not applicable in this case.

Thanks!

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4 Replies
AEsqu
Novice
760 Views

Is this the only way?

Create a new verilog file with this inside:

`define WITH_TH

 

and add this file in the quartus .qsf 

 

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YEan
Employee
744 Views
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AEsqu
Novice
741 Views

Hi Ean,

your answer is about creating a vqm file,

which is not the question.

Anyway, I used what I proposed after as a workaround.

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YEan
Employee
738 Views

Hi ,

I’m glad that your issue has been resolved. I'll now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts.

Thank you.

 

Regards,

Ean

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