verilog no warning when input wired to submodule output?

[Altera_Forum]

Hi, had a hard to find bug in my design, the cause went unnoticed since Quartus 9.1WE did not give any warning/error on the problem that boils down to this: 

 module test_v10(clk, o); input clk; input o; // should really be 'output o;' wire o; mod u1(.clk(clk), .out(o)); Is there some setting for Quartus to report such problems? (just thinking, maybe i unknowingly disabled it somewhere) Or do I make some other fundamental mistake in the code? :)

[Altera_Forum]

Most likely what Quartus did report was that a node had no driver, or that it was synthesizing away logic (because it wasn't connected to anything), or that it converted a tri-state buffer to an input or something. These would have been visible in the synthesis report and/or fitter report. 

 The code itself is not illegal. And ModelSim won't flag it as an error/warning either.  Jake

[Altera_Forum]

--- Quote Start ---  Hi, had a hard to find bug in my design, the cause went unnoticed since Quartus 9.1WE did not give any warning/error on the problem that boils down to this:  module test_v10(clk, o); input clk; input o; // should really be 'output o;' wire o; mod u1(.clk(clk), .out(o)); Is there some setting for Quartus to report such problems? (just thinking, maybe i unknowingly disabled it somewhere) Or do I make some other fundamental mistake in the code? :)  --- Quote End ---    Hi,  you should look for warnings like:  Warning: Design contains 2 input pin(s) that do not drive logic  Warning (15610): No output dependent on input pin "clk"  Warning (15610): No output dependent on input pin "o"  or  Warning: Output pins are stuck at VCC or GND  Warning (13410): Pin "test" is stuck at VCC  Kind regards  GPK