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Hai all,
Can anyone explain the SXT function in vhdl code? For example bp<=SXT(a,9)..I try to study from reference book and find others tutorial, but make me more confuse. Please help me :confused:Link Copied
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SXT performs a conversion of a vector to the specified size using sign extension, i.e. it extends the vector size by replicating the MSB into the added bits.
For example if you defined a : in std_logic_vector(5 downto 0); bp : out std_logic_vector(9 downto 0); and you have a = 101101 upon using bp = SXT(a,9) you'd get bp = 111101101- Mark as New
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Obviously this is only intended for std_logic_vectors that are storing signed values. You'll get odd results on unsigned values.
To make life a little less confusing (ie. not using std_Logic_vectors) I recommend using the numeric_std library where you can use the signed and unsigned types in the same file, and there is a function "resize" that does the same function, but works for both types.- Mark as New
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--- Quote Start --- Obviously this is only intended for std_logic_vectors that are storing signed values. You'll get odd results on unsigned values. To make life a little less confusing (ie. not using std_Logic_vectors) I recommend using the numeric_std library where you can use the signed and unsigned types in the same file, and there is a function "resize" that does the same function, but works for both types. --- Quote End --- Hai Cris72 and Tricky, Thanks for your explanation. If I have line code of bp<=SXT(a,9) + b where a and b is std_logic_vector(7 downto 0), bp is std_logic_vector(8 downto 0)? What the different with bp<= a+b?
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IIRC with both the numeric_std and the std_logic_(un)signed libraries, the result of an addition is of the same size than the biggest of the operands. In your case a and b are both 8 bits long, so a+b would also be 8 bits long, and you risk having an overflow. With the size extension the result of the operation is a 9 bit vector.

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