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vhdl don't care problem

Altera_Forum
Honored Contributor II
2,625 Views

Hello. I am making priority encoder in vhdl and I want to use process, case statement and 

don't care statement. 

This is my code and compile is done very well. but in model_sim, the output is always  

'000' even though when I changed input clock.. 

what's the problem? 

 

 

LIBRARY IEEE; 

USE IEEE.STD_LOGIC_1164.ALL; 

 

ENTITY enco is 

port( 

input : in std_logic_vector(7 downto 0);  

binary_out : out std_logic_vector(2 downto 0));  

end enco; 

 

ARCHITECTURE arc of enco is 

begin 

process(input) 

begin 

case input is 

when "00000001" => binary_out <= "000"; 

when "0000001-" => binary_out <= "001"; 

when "000001--" => binary_out <= "010"; 

when "00001---" => binary_out <= "011"; 

when "0001----" => binary_out <= "100"; 

when "001-----" => binary_out <= "101"; 

when "01------" => binary_out <= "110"; 

when "1-------" => binary_out <= "111"; 

when others => binary_out <= "000"; 

end case; 

end process; 

end arc;
0 Kudos
10 Replies
Altera_Forum
Honored Contributor II
873 Views

Rewrite it with, 

 

if 

elsif 

elsif 

... 

... 

else 

 

Statements. Drop the don't cares. Think about this, 

 

What is if (input1 = '-') then ... is it true or false?
Altera_Forum
Honored Contributor II
873 Views

I haven't used VHDL in ages but I don't think it supports don't cares in case statements until the 2008 version. So go into the Quartus settings for the project --> Analysis and Synthesis --> VHDL input --> select 2008 version

Altera_Forum
Honored Contributor II
873 Views

Ok, you cannot use '-' in case statements with older versions of VHDL, but newer versions of Quartus do support the matching case statement from 2008 (ie. using dont cares). 

 

If you have problems with this, you can always use the old fashioned method using the std_match function from the numeric_std library: 

 

if std_match(input, "00000001") then elsif std_match(input, "0000001-") then elsif std_match(input, "000001--") then --etc
Altera_Forum
Honored Contributor II
873 Views

I am using the quartus 12.0 version.. 

is the quartus version too old to use don't care statement i wrote in my code??
Altera_Forum
Honored Contributor II
873 Views

Q12 is the most up to date. In the menu, you need to set the VHDL version to 2008, or for modelsim, use the -2008 option on vcom when you compile the VHDL (what version of modelsim is it?) 

 

in Quartus: 

assignments -> settings -> analysis and synthesis settings -> VHDL input -> 2008 

 

The problem is for a while modelsim and quartus supported different things. You need modelsim 10.1 I think for full VHDL 2008 support.
Altera_Forum
Honored Contributor II
873 Views

just checked, modelsim 10.0 should support matching case statements, but you need to compile the code with the -2008 switch. Or modify your modelsim.ini so that  

 

VHDL93 = 2008 (its a silly variable name, but its old)
Altera_Forum
Honored Contributor II
873 Views

Hello.. I want to make priority encoder. and I need to use "don't care" 

the first code is working well. but when i tested in model_sim. 

the output is always "000". 

i thinks if input is "00001--" , and if I make the output "00000100" ,"00000101", 

"00000110" or "00000111", the output should be "2" = "010". but it's always "000". 

I use quartus2 version 12.0 and model_sim 12.0 (free_version) 

(someone said i should use std_match so i made second code using std_match, 

but it has error. what is the problem?) 

can anyone give me the priority encoder example using don't care "-"? 

I am doing this for 1 hours.. but i don't know what's wrong!! 

 

---------------------------------------------------------- 

---------------------------------------------------------- 

LIBRARY IEEE; 

USE IEEE.STD_LOGIC_1164.ALL; 

ENTITY enco is 

port( 

input : in std_logic_vector(7 downto 0);  

binary_out : out std_logic_vector(2 downto 0));  

end enco; 

ARCHITECTURE arc of enco is 

begin 

process(input) 

begin 

case input is 

when "00000001" => binary_out <= "000"; 

when "0000001-" => binary_out <= "001"; 

when "000001--" => binary_out <= "010"; 

when "00001---" => binary_out <= "011"; 

when "0001----" => binary_out <= "100"; 

when "001-----" => binary_out <= "101"; 

when "010-----" => binary_out <= "110"; 

when "1-------" => binary_out <= "111"; 

when others => binary_out <= "000";  

end case; 

end process; 

end arc; 

------------------------------------------------------------ 

------------------------------------------------------------- 

 

LIBRARY IEEE; 

USE IEEE.STD_LOGIC_1164.ALL; 

ENTITY enco1 is 

port( 

input : in std_logic_vector(7 downto 0); -- 8bit vector &#47484; &#51060;&#50857;&#54644; input0~input7&#47484; &#54620;&#48264;&#50640; &#47564;&#46316; 

binary_out : out std_logic_vector(2 downto 0)); -- 3bit vector &#47484; &#51060;&#50857;&#54644; input1,input2,input3&#47484; &#54620;&#48264;&#50640; &#50670;&#51020; 

end enco1; 

ARCHITECTURE arc of enco1 is 

begin 

process(input) 

begin 

if std_match(input, "00000001") then binary_out <= "000"; 

elsif std_match(input, "0000001-") then binary_out <= "001"; 

elsif std_match(input,"000001--") then binary_out<="010"; 

elsif std_match(input,"00001---") then binary_out<="011"; 

elsif std_match(input,"0001----") then binary_out<="100"; 

elsif std_match(input,"001-----") then binary_out<="101"; 

elsif std_match(input,"01------") then binary_out<="110"; 

elsif std_match(input,"1-------") then binary_out<="111"; 

else binary_out<="000"; 

end if; 

end process; 

end arc;
Altera_Forum
Honored Contributor II
873 Views

you didnt say what the error was with the std_match version. 

And did you set up the first version to VHDL 2008?
Altera_Forum
Honored Contributor II
873 Views

another way out. don't use don't care. 

 

if (input = "00000001") then binary_out <= "000"; 

elsif (input(7 downto 1) = "0000001") then binary_out <= "001"; 

elsif (input(7 downto 2) = "000001") then binary_out <= "010"; 

... 

...
Altera_Forum
Honored Contributor II
873 Views

if you want to include don't care (-) use this code this works.... 

 

library IEEE; 

use IEEE.STD_LOGIC_1164.ALL; 

use IEEE.NUMERIC_STD.ALL; 

entity enc is 

Port ( i_l : in STD_uLOGIC_VECTOR (7 downto 0); 

ei_l : in STD_uLOGIC; 

a_l : out STD_uLOGIC_VECTOR (2 downto 0); 

gs_l,eo_l : out STD_uLOGIC); 

end enc; 

architecture Behavioral of enc is 

begin 

process(i_l,ei_l) 

begin 

if (ei_l='0') then 

if std_match(i_l,"0-------") then a_l<="000"; gs_l<='0';eo_l<='1'; 

elsif std_match(i_l,"10------") then a_l<="001"; gs_l<='0';eo_l<='1'; 

elsif std_match(i_l,"110-----") then a_l<="010"; gs_l<='0';eo_l<='1'; 

elsif std_match(i_l,"1110----") then a_l<="011"; gs_l<='0';eo_l<='1'; 

elsif std_match(i_l,"11110---") then a_l<="100"; gs_l<='0';eo_l<='1'; 

elsif std_match(i_l,"111110--") then a_l<="101"; gs_l<='0';eo_l<='1'; 

elsif std_match(i_l,"1111110-") then a_l<="110"; gs_l<='0';eo_l<='1'; 

elsif std_match(i_l,"11111110") then a_l<="111"; gs_l<='0';eo_l<='1'; 

elsif std_match(i_l,"11111111") then a_l<="111"; gs_l<='1';eo_l<='0'; 

end if; 

else a_l<="111";gs_l<='1';eo_l<='1'; 

end if; 

end process; 

end Behavioral;
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