Your post is not well formatted and hard to read. Your code is also hard to follow. I dont think you really posted what the problem is.
Where is the testbench for this code? and can you post the whole code? then people might be able to simulate it themselves.
Did you know that VHDL supports base level primitives in the code? having your own components for each tends to lead to difficult to read and over-complicated code. Much easier to just write:
a <= b xor c;
etc.
