'*.vho not found' in Modelsim ALTERA

[remov_b4_flight]

Dear sirs,

At QuartusII 13.1 / Stratix3 project,

"DDR3 SDRAM Controller with UniPHY" IP on our design.

I finished synthesys and run modelsim 10.1d for RTL simulation,

After launched modelsim and do jobs in transcript window until 1st prompt.

I got error:

# vcom -93 -work work {*PATH*/*TO*/*PROJ/*IP_name*.vho}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
# ** Error: (vcom-7) Failed to open design unit file "*PATH*/*TO*/*PROJ*/*IP_name*.vho" in read mode.

Certainly do not have *.vho (IPFS FILES ?) file.

How to generate it and run simulation?

[AlanCLTan]

Hi,

You may refer to  https://www.intel.com/content/www/us/en/docs/programmable/730191/25-1/step-1-generate-gate-level-netlists.html for the steps to generate the .vho file.

Regards,

Alan

[remov_b4_flight]

Hi,

I ran EDA Netlist writer but only generated top level module vho file 

not IP module .vho file.

Is there option to do this?

[AlanCLTan]

Hi,

Please ensure IP Generation is complete. Make sure the IP core has been fully generated using the IP Catalog. This process should create the necessary simulation files.

1. Use the EDA Netlist Writer
Quartus uses the EDA Netlist Writer to generate simulation files like .vho (VHDL Output). For configuration steps:

• Go to Assignments > Settings > EDA Tool Settings > Simulation.
• Choose ModelSim-Altera as the tool.
• Set the Format to VHDL.
• Under Output, ensure Generate simulation netlist is checked.

2. After setting up the simulation tool:

Go to Tools > Run EDA Simulation Tool > RTL Simulation or manually run the EDA Netlist Writer via:

quartus_eda --simulation <project_name>

This typically generates the .vho file for the top-level design. However, if you need the .vho for the IP module itself, you may need to:

Open the IP folder (usually under ip/<ip_name>/simulation/). Look for .vho or regenerate using the IP generation tool with simulation files enabled.

Best regards,

Alan Tan

[RichardTanSY_Altera]

Are you planning to run RTL simulation or a post-fit functional simulation using a netlist?

Unfortunately, I am not familiar with UniPHY IP, however looking at the User Guide, the post-fit functional simulation does not seem to work for the UniPHY IP core. (check section 8.2.8. Post-fit Functional Simulation)

It appears that the post-fit netlist for designs containing UniPHY IP is a hybrid—gate-level for the FPGA core and RTL-level for the external memory interface IP.

https://www.intel.com/content/www/us/en/docs/programmable/683385/17-0/simulation-walkthrough-with-uniphy-ip.html

You can refer to the simulation walkthrough in the User Guide (link above), using an example design that can be generated with the IP core. Once you're familiar with the simulation flow, cross-check it against your own design to identify any discrepancies.

Additionally, do you use other IP in your design? Which specific IP is causing below error?
Could you provide the error log/transcript ? 

# ** Error: (vcom-7) Failed to open design unit file "*PATH*/*TO*/*PROJ*/*IP_name*.vho" in read mode.

Regards,

Richard Tan

[RichardTanSY_Altera]

Hi,

Do you have any further inquiries regarding this case? 

Regards,

Richard Tan

[RichardTanSY_Altera]

We noticed that we haven't received a response from you regarding the latest previous question/reply/answer, and will now transitioning your inquiry to our community support. We apologize for any inconvenience this may cause and we appreciate your understanding.

If you have any further questions or concerns, please don't hesitate to reach out. Please login to https://supporttickets.intel.com/s/?language=en_US, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

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Best Regards,

Richard Tan