what does tri1, tri0

[Altera_Forum]

How tri1 and tri0 are implemented in quartus II. Can't understand results from synthesized code; 

  module main3 (cols,LEDG,rows) ;  // ------------ Port declarations --------- // input tri0 [3:0] cols;  output reg [3:0] rows; initial begin rows = 4'b1111; end // -------- Component instantiations -------// output wire [3:0] LEDG;  assign LEDG = cols;  endmodule   Rows and cols are gpio pins which are floating, not connected to anything (GPIO_1 DE2 board). Result: LEDG[3:0] are lighting, how can cols have HIGH level when they should be pull downed? I can even turn off LEDG by touching one finger pins and other finger SD card metalic case on board which is grounded. So there are negligible voltage and no pull down I think. If there would be any pull down implemeted how should RTL schema look like ( I attach this code RTL schema).

[Altera_Forum]

I'm not 100% sure, but I believe Quartus ignores pull up/down input attributes in Verilog. 

You must set these I/O features in the pin assignment editor. Then, the behaviour you observed makes sense, since those input pins are unbiased.

[Altera_Forum]

I'm pretty sure Quartus ignores tri1/tri0 directives. 

 However, with regards to what you're trying to do with your DE2 board - you don't have any internal pull-down options anyway.  You don't say which flavour of DE2. However, for the Cyclone II version there is no option for any pulls in the FPGA. I/O pins have weak pull-ups active before and during configuration. From the Cyclone II datasheet:  --- Quote Start ---  In user mode, the user I/O pins no longer have weak pull-up resistors and function as assigned in your design.  --- Quote End ---    It's a similar story for the Cyclone IV DE2 boards:   --- Quote Start ---  All I/O pins have an option to enable weak pull-up except the configuration, test, and JTAG pins. The weak pull-down feature is only available for JTAG TCK.  --- Quote End ---    So, unfortunately, there is no option for internal pull-downs with the hardware you're using.  Cheers, Alex

[Altera_Forum]

That is one of the behavioral-only statements and I think it is not synthesizable. 

 You have to understand that Verilog was written oritinally as a netlisting language. Therefore they put in all kinds of structures that people put in chip design at the time and also looking a bit forwards. Digital logic using weak pull-ups was common in the 70's and 80's and it was to reduce the cost of the circuit by eliminating a lot of PMOS transistors. Today transistors are cheap, so this kind of design is restricted to just small niches.  Now, in synthesis world, you old build circuits that are very structured, use standard cells (ASIC) or FPGA LUTs. Then you would never have a weak pull-up. It is unpredictable what a synthesis tool will do with that. Will they consider it a wire, just give an error message, ignore it all together. There are synthesis tools that understand tri-state buffers to build tri-state busses but that is for ASICs, not for FPGAs.  Now, of course, to simulate in your behavioral testbench it is ok to do such things. So if you have a weak pull-up on your PCB, you can use tri, trireg, or perhaps a simple type "wire" and then use a PMOS component to connect it to supply1 and model your board in your testbench, but don't put these statements on anything that Quartus will be synthesizing..  Synthesis does some odd magic at times and often is not what makes sense, especially if you code devices like flops and latches not strictly how they should be written to make sure it properly converts the RTL to the structures you have. Check out http://www.altera.com/literature/hb/qts/qts_qii51007.pdf for proper coding rules on different components if you want to know more about this.