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what is the problem?

gAcqu
Beginner
223 Views

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_unsigned.all;

ENTITY add_three_numbers IS

PORT ( clock : IN STD_LOGIC;

A, B, C : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

sum : OUT STD_LOGIC_VECTOR(9 DOWNTO 0));

END add_three_numbers;

ARCHITECTURE Behavior OF add_three_numbers IS

-- Registers

SIGNAL reg_A, reg_B, reg_C : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL reg_sum : STD_LOGIC_VECTOR(9 DOWNTO 0);

ATTRIBUTE keep : boolean;

ATTRIBUTE keep OF reg_A, reg_B, reg_C, reg_sum : SIGNAL IS true;

BEGIN

PROCESS ( clock )

BEGIN

IF (clock’EVENT AND clock = ‘1’) THEN

reg_A <= A;

reg_B <= B;

reg_C <= C;

reg_sum <= ("00" & reg_A) + ("00" & reg_B) + ("00" & reg_C);

END IF;

END PROCESS;

sum <= reg_sum;

END Behavior;

 

 

 

 

Error (10500): VHDL syntax error at add_three_numbers.vhd(18) near text ’

Error (10500): VHDL syntax error at add_three_numbers.vhd(18) near text "’"; expecting ")", or ","

Error (10500): VHDL syntax error at add_three_numbers.vhd(18) near text ‘

Error: Quartus II Analysis & Synthesis was unsuccessful. 3 errors, 1 warning

   Error: Peak virtual memory: 303 megabytes

   Error: Processing ended: Fri Apr 03 18:52:58 2020

   Error: Elapsed time: 00:00:07

   Error: Total CPU time (on all processors): 00:00:01

Error: Quartus II Full Compilation was unsuccessful. 5 errors, 1 warning

0 Kudos
2 Replies
imarz1
Novice
135 Views

You must have typed invisible ASCII character in the line:

IF(clock'EVENT AND clock = '1') THEN 

 

So, just delete that line completely, and re-write it.

Also, good to add as first line of code: library IEEE;

gAcqu
Beginner
135 Views
Reply