Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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17268 Diskussionen

what's wrong between QII6.1 and QII9.0

Altera_Forum
Geehrter Beitragender II
1.458Aufrufe

wire a_cs_n; 

wire b_cs_n; 

assign a_cs_n = (addr[19:18]==2'b01)? 1'b0 : 1'b1; 

assign b_cs_n = (addr[19:18]==2'b00 && addr[17:16]==2'b10) ? 1'b0 : 1'b1; 

assign dout = ({16 {a_cs_n}} | 16'haaaa ) & ({16 {b_cs_n}} | 16'hbbbb) ; 

 

With QII 6.1,dout can get 16'haaaa or 16'hbbbb.But with Qii 9.0,dout cannot get 16'haaaa。 

We don't change the code.But get the different result. 

Why? 

Thank you very much!
0 Kudos
2 Antworten
Altera_Forum
Geehrter Beitragender II
769Aufrufe

 

--- Quote Start ---  

wire a_cs_n; 

wire b_cs_n; 

assign a_cs_n = (addr[19:18]==2'b01)? 1'b0 : 1'b1; 

assign b_cs_n = (addr[19:18]==2'b00 && addr[17:16]==2'b10) ? 1'b0 : 1'b1; 

assign dout = ({16 {a_cs_n}} | 16'haaaa ) & ({16 {b_cs_n}} | 16'hbbbb) ; 

 

With QII 6.1,dout can get 16'haaaa or 16'hbbbb.But with Qii 9.0,dout cannot get 16'haaaa。 

We don't change the code.But get the different result. 

Why? 

Thank you very much! 

--- Quote End ---  

 

 

Hi, 

 

I run a test with Quartus II 9.0 (Full version). I looks pretty in my project. 

I have the project attached. Maybe I made a mistake in the project ? 

 

Kind regards 

 

GPK
Altera_Forum
Geehrter Beitragender II
769Aufrufe

Why don't you write: 

always @ (*) begin 

if (a_cs_n) dout <= 16'haaaa; 

if (b_cs_n) dout <= 16'hbbbb; 

end
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