Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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when I generated PLL ip before, a file name _inst.v was generated, so I can copy the example to my script. but the new one in quartus 17/18, the file seems missing. where can I find the example file?

ZLu001
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Vicky1
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Hi Zen, Please follow the below steps, 1. "File" Menu -> "Open"-> PLL.v(IP created file) 2. Then Go to "File" ->"Create/ Update" -> "Create Verilog instantiation Template files for current file" 3.Check the "PLL.inst.v" file under project directory. Let me know if this has helped to resolve the issue. Regards, Vikas
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ZLu001
Novice
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Hi, Vikas.

when I use Quartus17 to open the PLL file( my is base_clock.v) the megawizad was appear and then the "Create Verilog instantiation Template files for current file" is grey out.

then I tried Quartus18, the file was opened at editor window and as you told, everything is fine.

 

Thank you very much.

 

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