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ZLu001
Novice
436 Views

when I generated PLL ip before, a file name _inst.v was generated, so I can copy the example to my script. but the new one in quartus 17/18, the file seems missing. where can I find the example file?

 
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2 Replies
Vicky1
Employee
36 Views

Hi Zen, Please follow the below steps, 1. "File" Menu -> "Open"-> PLL.v(IP created file) 2. Then Go to "File" ->"Create/ Update" -> "Create Verilog instantiation Template files for current file" 3.Check the "PLL.inst.v" file under project directory. Let me know if this has helped to resolve the issue. Regards, Vikas
ZLu001
Novice
36 Views

Hi, Vikas.

when I use Quartus17 to open the PLL file( my is base_clock.v) the megawizad was appear and then the "Create Verilog instantiation Template files for current file" is grey out.

then I tried Quartus18, the file was opened at editor window and as you told, everything is fine.

 

Thank you very much.

 

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