Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15322 Discussions

when I generated PLL ip before, a file name _inst.v was generated, so I can copy the example to my script. but the new one in quartus 17/18, the file seems missing. where can I find the example file?

ZLu001
Novice
528 Views
 
0 Kudos
2 Replies
Vicky1
Employee
128 Views
Hi Zen, Please follow the below steps, 1. "File" Menu -> "Open"-> PLL.v(IP created file) 2. Then Go to "File" ->"Create/ Update" -> "Create Verilog instantiation Template files for current file" 3.Check the "PLL.inst.v" file under project directory. Let me know if this has helped to resolve the issue. Regards, Vikas
ZLu001
Novice
128 Views

Hi, Vikas.

when I use Quartus17 to open the PLL file( my is base_clock.v) the megawizad was appear and then the "Create Verilog instantiation Template files for current file" is grey out.

then I tried Quartus18, the file was opened at editor window and as you told, everything is fine.

 

Thank you very much.

 

Reply