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why different simulation outputs modelsim and simulation wave editor for ring osc..

Altera_Forum
Honored Contributor II
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Hello to everyone. 

 

I apologize for disturbing you. I am trying to modeling ring oscillator in FPGA. You can see my design details in attached photo files.  

 

 

  • At first modeled it schematically(photo1) then i run timing simulation it via simulation waveform editor/university program tools. 

 

With this method i can see timing delays outputs(photo2 and photo3). when simulation results expanded outputs  

 

 

  • Then i want to see my outputs delays in modelsim. For this purpose i convert my schematic design to .vhd file(file>create/update>create hdl design...). Then i use gate level simulation tool in quartus for modelsim. .... When I look at the results(photo4-->results, photo5-->zooming results) there is a problem. 

 

The outputs of modelsim and university program quite different from each other. In modelsim the delay for the next output from the previous one logic delays periodically  

increasing(photo 4 photo 5). But in simulation waveform editor/university program ring oscillator outputs logic delays not periodic(photo 2 photo3).  

What is the main reason for this situation and which result is correct? i couldnt decided.
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Altera_Forum
Honored Contributor II
431 Views

Hi, 

 

Can you share the .bdf file? 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
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Altera_Forum
Honored Contributor II
431 Views

Ok, thanks for your interest, i sent it.

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Altera_Forum
Honored Contributor II
431 Views

Hi, 

 

Yes, In simulation result we can see the difference. 

This is because of the conversion(.bdf to .vhd/.v) which we are doing. 

The conversion is adding some extra delay/logic which can be seen in RTL viewer because of which we are getting the different results. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
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