wire Verilog to VHDL

Altera_Forum · ‎02-21-2012

Can anyone help me translate this from Verilog to VHDL:

wire [4:0] sub_wire0;

wire [0:0] sub_wire5 = 1'h0;

wire [0:0] sub_wire2 = sub_wire0[0:0];

wire [1:1] sub_wire1 = sub_wire0[1:1];

wire c1 = sub_wire1;

wire c0 = sub_wire2;

wire sub_wire3 = inclk0;

wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};

Altera_Forum · ‎02-21-2012

This should do it:


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY test IS
    PORT (
        inclk0 : IN std_logic
        );
END ENTITY test;
ARCHITECTURE rtl OF test IS
    SIGNAL sub_wire0 : std_logic_vector(4 DOWNTO 0);
    SIGNAL sub_wire5 : std_logic := '0';
    SIGNAL sub_wire2 : std_logic_vector(0 DOWNTO 0);
    SIGNAL sub_wire1 : std_logic_vector(1 DOWNTO 1);
    SIGNAL c1        : std_logic;
    SIGNAL c0        : std_logic;
    SIGNAL sub_wire3 : std_logic;
    SIGNAL sub_wire4 : std_logic_vector(1 DOWNTO 0);
    
BEGIN  -- ARCHITECTURE rtl
    sub_wire2(0) <= sub_wire0(0);
    sub_wire1(1) <= sub_wire0(1);
    c1 <= sub_wire1(1);
    c0 <= sub_wire2(0);
    sub_wire3 <= inclk0;
    sub_wire4 <= sub_wire5 & sub_wire3;
END ARCHITECTURE rtl;

But to be honest this code doesn't make much sense.

Altera_Forum · ‎02-21-2012

after a quick glance this looks correct

the code looks like it's machine generated to me, which is why it doesn't make sense

Altera_Forum · ‎02-22-2012

Is there any tool to convert from verilog to vhdl.

i have synapticad but i dont know how to convert it.

give some tools for HDL conversion.

Altera_Forum · ‎02-23-2012

vasireddyrajesh3 (http://www.alteraforum.com/forum/member.php?u=56700): Yes, X-HDL is a tool, but it wont work for files over 1024 bytes :mad:

Altera_Forum · ‎02-23-2012

schmalisch (http://www.alteraforum.com/forum/member.php?u=1078): Thank you for your help :)

Altera_Forum · ‎02-25-2012

Thank you for the info.