wire assignment in verilog

[junyoung2]

Hello, I have a question while I was writing the code. I made a code wire [15:0] A; and I declared input B; and I declared this signal as assign A = {8{B}};. When I declared this, the top 8 bits of signal A would be filled with 0, so why would it be filled with 0? Shouldn't it be filled with z or x??

[RichardTanSY_Altera]

Please allow us some time to look into.

Thank you for your time and patience.

Regards,

Richard Tan

[KennyTan_Altera]

Hi, can you check your email for this? As this require long explanation from Questa support.

[KennyTan_Altera]

Did you manage to check your email? If yes, please help to reply in the email for the confirmation.

[KennyTan_Altera]

this case is close internally.