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Hi i experience some confusing behavior when i work with Qsys and Quartus to create/modify vhdl files used in IP components used in qsys. Here is what i do..
1) edit vhdl file used in Component "MySomething" in Quartus (This file is included in my Quartus project, not sure if it has to be ? properly not) 2) to update my system with the change, i open Qsys and click generate HDL 3) remove old .qip file in Quartus project and add new to project 4) "Ctrl+L" to start compilation 5) download .sof file 6) Open my NIOS debug project 7) right click on project_bsp->index->rebuild all 8) right click on project_bsp->NIOSII->generate BSP 9) right click on project->index->rebuild all 10) start debugger via JTAG is this the correct work flow for update of IP components ? heres the Problem. when i make an update to my vhdl file and saves it, then start Analysis and Synthesis, it used another version the component file. Where is this file stored ? how do i update it ? thanks in advanceLink Copied
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hi just noticed "Reusing file"
https://www.alteraforum.com/forum/attachment.php?attachmentid=10812 can anybody please explain whats in those files ?- Mark as New
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Hello,
--- Quote Start --- when i make an update to my vhdl file and saves it, then start Analysis and Synthesis, it used another version the component file. Where is this file stored ? how do i update it --- Quote End --- When ever you select 'Generate HDL' for your system in Qsys, Qsys copies your files from original location to 'submodules' folder in your project. 'submodules' folder is automatically created under folder having same name as your Qsys system name. And these files are used during compilation in Quartus. So if you edit your original file, it would not get reflected during Analysis and Synthesis. If you edit your original file, you need to reopen your Qsys and select 'Generate HDL' option again to let Qsys copy your updated file into 'submodules' folder. I hope this helps. Cheers, Bhaumik- Mark as New
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thank you that helps..

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