Layout documentation for TALIVERDE

[jungsoolim]

We have found the TALIVERDE schematics as below:

Lewisburg PCH in Endpoint Only (EPO) Mode – Reference Schematics
ID: 560351

Additionally, could we please get the layout documentation for TALIVERDE as well?

[Ronny_G_Intel]

Hi Jungsoo,

Let me do some investigation and I will get back to you as soon as possible.

Regards,

Ronny G

[Ronny_G_Intel · Accepted solution]

Hi Jungsoo,

Please find below the link to schematics for:

TALIVERDE

TECHNOLOGY AND INTEGRATED 10 GBE / 1 GBE

LEWISBURG CHIPSET: ENDPOINT ONLY (EPO) MODE

https://www.intel.com/content/www/us/en/secure/content-details/560351/lewisburg-pch-in-endpoint-only-epo-mode-reference-schematics.html?wapkw=taliverde&DocID=560351

Please note that this information is classified as Intel Confidential, requiring the appropriate level of permissions for access.

I also created an IPS ticket to address this issue, so I am closing this community post. Please use the IPS ticket to follow up on this issue.

Regards,

Ronny G