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I am currently designing with a MAX10 FPGA. For an unused I/O bank, I intend to connect its VCCIO to a suitable power rail without including any bulk or decoupling capacitors. Would this approach be acceptable?
device: 10M08SAE144
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Hi,
You posted in the Intel® QuickAssist Technology (Intel® QAT) forum. For FPGA questions, see the yellow banner at the top of the community pages.
Regards,
Diego V.
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