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Rink
Novice
496 Views

Accessing the Global Timer from the FPGA (Cyclone V SoC)?

Is it possible for the FPGA logic side to access the Global Timer?

Does it involve a memory-access via the FPGA–to–HPS bridge perhaps?

I am interested in capturing the value to resolve event timing across the FPGA and HPS boundaries?

Thanks!

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LeonWaksman
Super User
113 Views

Rink
Novice
113 Views

Sorry - I thought I put it in the wrong section. Only noticed the 'hps' topic at the bottom of the web page after I posted the first one.

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